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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
PM7380
FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU
REFERENCE DESIGN
PRELIMINARY ISSUE 1: OCTOBER 1999
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
REVISION HISTORY Issue No. 1 Issue Date Feb 2000 Details of Change Document created.
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 2 3 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATION............................................................................... 1
FEATURES .............................................................................................. 3 BLOCK DESCRIPTION ........................................................................... 4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 REFERENCE DESIGN ................................................................. 4 DS3 LIU......................................................................................... 6 LOCAL-PCI BRIDGE..................................................................... 6 LOCAL-PCI SEEP......................................................................... 8 TEMUX.......................................................................................... 8 FREEDM-32P672........................................................................ 10 PCI-PCI BRIDGE .........................................................................11 PCI BUS INTERFACE TO THE HOST PROCESSOR AND PACKET MEMORY ..................................................................... 13 TIMING BLOCK........................................................................... 15 POWER BLOCK ......................................................................... 16 FRONT PANEL ........................................................................... 16
4
DESIGN ISSUES ................................................................................... 17 4.1 DS3 LIU....................................................................................... 17 4.1.1 TDK78P2241 3.3V VERSUS 5V ...................................... 17 4.1.2 POWER SUPPLY ............................................................. 17 4.1.3 TRANSFORMERS............................................................ 17
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
4.1.4 TERMINATION RESISTORS ........................................... 17 4.2 TEMUX........................................................................................ 17 4.2.1 POWER SUPPLY ............................................................. 17 4.2.2 DE-COUPLING................................................................. 18 4.3 FREEDM-32P672........................................................................ 18 4.3.1 POWER SUPPLY ............................................................. 18 4.3.2 TIMING ............................................................................. 18 4.3.3 DE-COUPLING................................................................. 18 4.4 PCI 9054 ..................................................................................... 18 4.4.1 POWER SUPPLY ............................................................. 18 4.4.2 CPLD ................................................................................ 18 4.5 PCI 21152.................................................................................... 20 4.5.1 POWER SUPPLY ............................................................. 20 4.5.2 TIMING ............................................................................. 20 4.6 4.7 4.8 TIMING DISTRIBUTION ............................................................. 20 POWER REQUIREMENTS......................................................... 20 CONNECTORS ........................................................................... 21 4.8.1 JTAG PORT...................................................................... 21 4.8.2 PCI CONNECTOR............................................................ 21 4.8.3 HEADERS ........................................................................ 22 5 SOFTWARE INTERFACES ................................................................... 23 5.1 5.2 5.3 GENERAL OVERVIEW ............................................................... 23 TEMUX........................................................................................ 23 FREEDM-32P672........................................................................ 23
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
5.4 5.5 5.6 6
FREEDM-32P672 PCI CONFIGURATION.................................. 23 PCI 9054 CONFIGURATION....................................................... 24 PCI 21152 CONFIGURATION..................................................... 25
COMPONENT SELECTION .................................................................. 29 6.1 6.2 6.3 6.4 PCI-PCI BRIDGES ...................................................................... 29 OSCILLATOR.............................................................................. 29 DE-COUPLING AND BYPASS CAPACITORS ............................ 30 RESISTORS................................................................................ 30
7 8 9 10 11 12
GLOSSARY ........................................................................................... 31 REFERENCES....................................................................................... 32 DISCLAIMER ......................................................................................... 34 APPENDIX A: SCHEMATIC................................................................... 35 APPENDIX B: BILL OF MATERIALS ..................................................... 43 APPENDIX C: VHDL CODE FOR GLUE LOGIC ................................... 48
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
LIST OF FIGURES FIGURE 1 - FRAME RELAY INTER-NETWORKING OVERVIEW.................... 2 FIGURE 2 - FREEDM-32P672 WITH DS3 LIU BLOCK DIAGRAM .................. 4 FIGURE 3 - REFERENCE DESIGN BUS ARCHITECTURE............................. 5 FIGURE 4 - DIRECT SLAVE ADDRESS SPACE MAPPING............................. 7 FIGURE 5 - PCI ADDRESS MAP .................................................................... 14 FIGURE 6 - TEMUX READ TIMING DIAGRAM .............................................. 19 FIGURE 7 - TEMUX WRITE TIMING DIAGRAM ............................................ 19
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - DS3 LIU CONFIGURATION .......................................................... 6 - PCI 9054 LOCAL ADDRESS SPACE ALLOCATION ..................... 7 - PCI 21152 CONFIGURATION SPACE (MAIN REGISTERS) ...... 12 - COMPONENT POWER CONSUMPTION ................................... 21 - PCI 9054 CONFIGURATION REGISTERS VALUES .................. 25 - PCI21152 INITIALIZATION OF CONFIGURATION REGISTERS 26 - PCI21152 MEMORY-MAPPED I/O SPACE REGISTERS............ 27 - PCI21152 I/O ADDRESS SPACE REGISTERS........................... 28 - OSCILLATOR VENDORS............................................................ 29
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
1
INTRODUCTION The FREEDM-32P672 WITH DS3 LIU Reference Design entails the interfacing of PM7380 FREEDM-32P672 and TDK78P2241 DS3 LIU via PM8315 TEMUX. This document provides an application example for FREEDM-32P672 encompassing the reception and transmission of DS3 data, multiplexing 28 DS1 streams, and finally downstreaming HDLC data to a PCI bus.
1.1
Purpose This design provide interfacing details to assist designers of routers and frame relay switches in building DS3 applications using PMC-Sierra's FREEDM32P672 and TEMUX.
1.2
Scope This document describes interfacing of DS3 data stream to a 32-bit PCI bus using a DS3 LIU, PMC TEMUX, PMC FREEDM-32P672, and PCI bridges. Functional blocks of this design are separately explained and implementation details are provided.
1.3
Application The FREEDM-32P672 and DS3 LIU application lies within the realms of Frame relay networking. Frame relay is a multiplexed data networking technology - supporting connectivity between user equipment and the public frame relay network. The frame relay protocol supports data transmission over a connectionoriented path and enables the transmission of variable-length data units over an assigned virtual connection. Frame relay technology can be used in LAN interconnection, Internet access and Internet backbones using link speeds ranging from 9600 baud to the DS3 rate. Figure 1 illustrates a typical implementation of a frame relay interface (FRI) and a frame relay user to network interface (FUNI) using T1, E1 and DS3 rates.
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
Figure 1
- Frame Relay Inter-networking Overview
ISP
Dial-up Access Server Frame Relay Access Switch
INTERNET
Frame Relay Switch
IP Router
ATM Switch FUNI FRI PCI Bus PM7375 LASAR-155 PM7345 S/UNI-PDH ATM T1, E1 T3, E3 PM7380 FREEDM Processor
Packet Memory
PM8315 TEMUX
DS3 LIU
ATM OC-3 Switch Fabric
T3
Equipment such as routers, T1 multiplexers, nodal processors, packet switches, front end processors, and packet assemblers/dissemblers need to support the frame relay interface in order for them to be connected to a private or a public frame relay network. In this application, the DS3 LIU enables interfacing to a T3 line. The FREEDM32P672 provides the HDLC processing which is used in Frame Relay.
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
2
FEATURES * * * * * * Interfaces to a DS3 link carrying channelized or unchannelized data Able to support up to 672 bi-directional HDLC channels assigned to a maximum of 28/21 channelized T1/E1 links respectively Interfaces to a PCI bus (33MHz) which as a host processor and packet memory Control and monitoring of the TEMUX and FREEDM-32P672 devices is done by the host microprocessor via the PCI bridges and PCI interface JTAG access to the TEMUX and FREEDM-32P672 is achieved via the PCI interface Front panel LEDs for power and other status reports
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
3 3.1
BLOCK DESCRIPTION Reference Design The FREEDM-32P672 with DS3 LIU reference design card demonstrates an application of interfacing between T1/E1 and DS3 data streams, which is commonly found in Frame Relay to ATM internetworking or PPP processing applications. Frame relay packets arrive and depart at the DS3 LIU. Multiplexing/Demultiplexing of DS3 o DS1 data streams occurs in the TEMUX. The FREEDM-32P672 performs HDLC processing and interfacing to the PCI bus, which has the host processor and packet memory. Figure 2 illustrates the reference design and its sub-blocks, which are explained in the following sections. Figure 2 - FREEDM-32P672 with DS3 LIU Block Diagram
Tx Bantam LOUT+ LOUT LIN + LIN TPOS TPOS TNEG TCLK TICLK XCLK CTCLK 44.736 MHz 37.056 MHz
OSCILLATORS
Bantam Rx
DS3 LIU
TDK78P2241
TNEG TCLK
12.352/16.384 MHz
RPOS RNEG RCLK
RPOS RNEG RCLK 28 28
TEMUX
Local Bus
EESK EEDO EESK EEDO A [13:0] D [7:0] 14 8 A [13:0] D [7:0] RDB WRB CSB RSTB INTB TRSTB
ED [1:28] ECLK [1:28] ID [1:28] ICLK [1:28]
TD [1:28] TCLK [1:28]
PM8315
28 28
RD [1:28] RCLK [1:28]
SEEP
EEDI EECS EEDI EECS
Local-PCI Bridge
PLXPCI9054
RDB WRB CSB RSTB INTB
FREEDM-32P672
PM7380
TRSTB
TCLK
TCLK
TMS
TMS
TDO
TDO
TDI
LEDs
TDI
Secondary PCI Bus
Power Block
RESET
5V
PCI-PCI Bridge
IntelPCI21152
32 32
62
A/B 51 50
A/B 13 12
1
PCI Bus to other devices
Primary PCI Bus
Host Processor
Packet Memory (RAM)
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
Figure 3 shows the bus architecture in the reference design. The PCI-PCI Bridge is necessary to satisfy PCI bus specifications, refer to document [7]. Figure 3 - Reference Design Bus Architecture
FREEDM32P672* TEMUX** CPLD** Local-PCI Bridge*
* ** PCI Device Non PCI Device
PCI-PCI Bridge*
Local Bus
CLK Width D Width A Signaling 8 MHz 8 bits 14 bits 3.3 V
Secondary PCI Bus
CLK 33 MHz Width A/D 32 bits Signaling 3.3 V
Primary PCI Bus
CLK 33 MHz Width A/D 32 bits Signaling 5 V
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
3.2
DS3 LIU Interfacing to a T3 line is accomplished through the use of a TDK 78P2241 E3/DS3/STS-1 line interface transceiver IC, transformers, and several passive components. The line interface unit operates a DS3 signal at 44.736 Mbs. The receiver recovers the clock and positive and negative data from a B3ZS/HDB3 encoded AMI signal. The transmitter generates an AMI pulse, which can drive a 75 coaxial cable. The /ENDEC pin must be set high to disable NRZ logic data generation. The TPOS/RPOS and TNEG/RNEG send and receive Positive and Negative AMI signal respectively. There is an onboard equalizer for combating intersymbol interference. There is also an internal PLL for locking on to the frequency of incoming data eliminating the need for high precision external clock. Table 1 indicates the main parameter configurations for the desired behavior of the TDK78P2241. Refer to the datasheet [15] for further information. The physical interface to the DS3 line will be via 75 Bantam connectors. Table 1 - DS3 LIU Configuration
RFO 5.23 k /LPBK High /E3 High RTT 301 MON Low RTR 75 ICKP Low CLF 0.047 F /ENDEC High TXEN High
Pin/Component Value Pin/Component Value
LBO Cable < 225 ft High Cable 225 ft Low
3.3
Local-PCI Bridge The Local to PCI Bridge used is PLX Technology's PCI9054 PCI Bus Master I/O Accelerator (PCI 2.2 compliant). This device interfaces the TEMUX to the Secondary PCI bus. Along with the PCI-to-PCI bridge, the PCI9054 enables the TEMUX to be accessible from the host processor. The PCI9054 provides master and target mode interfaces, of which the latter is used in this design, i.e. the PCI9054 is a target on the (Secondary) PCI bus and a master on the Local bus. The PCI9054 supports 32-bit wide, 33MHz PCI bus interfacing. The Local bus interface of the PCI9054 is generic and very flexible, supporting 8, 16, and 32-bit data transfers operating in multiplexed or non-multiplexed modes, with big/little Endian conversion capabilities at a clock rate asynchronous to the PCI bus. The device operates in 3 different modes, M, C, and J, of which, C is used in this design. Mode C provides a non-multiplexed interface on the Local side. In mode C, Direct Slave Transfer facilitates PCI access to the Local space. Read and
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
write operations occur in terms of single transfer accesses to the Local space. Therefore, a mapping must be configured between the PCI space and the Local space. Direct Slave PCI-to-Local address mapping could be configured in any of the 3 distinct user-definable address spaces that are provided by the PCI9054. In this design, only one partition is required for the TEMUX. A 14-bit address and an 8-bit data bus are required by the TEMUX. Hence, the Local data bus is configured as 8-bits, non-multiplexed, big Endian, non-burst, and non-prefetchable. Configuration of bus width is done by hardware using the LBEB<3.0> or by software in the Bus Region Descriptors for PCI-to-Local Accesses register. The Local address spaces are allocated during initialization as in Table 2. This Local mapping allows address translation from the PCI Address Space to the Local Address Space. Table 2 - PCI 9054 Local Address Space Allocation Function TEMUX internal registers None None
Address Space 0 1 ROM
Configuration is achieved via a serial EEPROM data download after power up and/or reset. After a PCI reset, the loaded software maps the Local Address space into the PCI Address space by programming the Local Address Range and PCI Base Address registers (since Address Space 0 is used, the registers are LAS0RR and LAS0BA). See Figure 4. Figure 4 - Direct Slave Address Space Mapping
PCI Address Space PCI Base Address Local Base Address Range Local Address Space
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The PCI9054 also has an internal wait state(s) generator for timing of the address spaces. The Local bus is clocked at 8MHz by an on board oscillator. A CPLD houses some glue logic, which is required to interface the PCI9054 to the TEMUX. Refer to the PCI9054 datasheet [9] for more information. 3.4 Local-PCI SEEP The NM93CS56L Serial EEPROM (2Kbit deep) from National Semiconductor is used to store configuration information for the PCI9054 bridge. PLX Technology recommends this specific SEEP; moreover it is suitable with the PCI9054 because it supports sequential read operations. The SEEP can be programmed over the PCI bus or Local bus, or by a Data I/O programmer, (in the latter case, the SEEP is socketed into the board.) In this design, the Data I/O programmer method is assumed. (The SEEP can also be programmed using the VPD function - refer to the PCI9054 datasheet [9] for details.) The PCI9054 detects the SEEP and reads the first LWORD. Upon detection of programmed data, the configuration data is loaded into the PCI9054. Refer to the PCI9054 datasheet [9] and the NM93CS56L datasheet [1] for detailed information on the format of the configuration data stored in the SEEP. 3.5 TEMUX The TEMUX is a feature rich monolithic device, which integrates 28 T1 framers or 21 E1 framers and a full-featured M13 multiplexer with a DS3 framer. It is software configurable via access to its configuration registers. A generic microprocessor can be used with the address lines A [13:1] and data lines D [7:0]. However, in this reference design, the configuration registers are accessed via the PCI bus and brides, hence configured by the host processor. The DS3 LIU interfaces to the DS3 framer sub block in the TEMUX, which asynchronously multiplexes/demultiplexes 28 T1/21 E1 streams to/from a serial DS3 (44.736 Mbs) data stream. The framer in each direction has a positive (TPOS/RPOS) and a negative (TNEG/RNEG) signal and its own clock (TCLK/RCLK). Set the OPMODE[1:0] bits in the Global Configuration register to configure the TEMUX as a DS3 framer. Although the device can support SBI bus interface, it is used here with only one FREEDM-32P672 and it is serially connected. Each of the ingress (ID [1:28]) and egress (ED [1:28]) data streams has its own clock signal (ICLK [1:28]/ECLK [1:28]). In the case of Ingress direction, frame pulse signals are not used.
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In the Egress direction, the TEMUX is operated in the Clock Master: NxChannel mode; modes are selected via the EMODE[2:0] bits in the T1/E1 Egress Serial Interface Mode Select register. For the Ingress direction the TEMUX is operated in the Clock Master: Full T1/E1 mode, which is selected via the IMODE[1:0] bits and INXCHAN[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. The TEMUX requires a Transmit Input Clock (TICLK = 44.736MHz) for the transmit direction and a Crystal Clock (XCLK = 37.056MHz) for timing many of the T1/E1 sub-blocks. Moreover, it needs a Common Transmit Clock (CTCLK = 12.352MHz (T1) 16.384MHz (E1)) for operation in Master modes. The receiving/sending DS3 framers support B3ZS encoded signal, detect/insert RED alarm, AIS and idle signal, and FERF. The framers are off-line framers supporting OOF and COFA events. The C-bit parity FEAC channel and the path maintenance data link are also supported. The framers detect/insert parity or path parity errors, F-bit and M-bit errors, invalid X-bits, P-bits, and C-bits, LCV, or EXZ. In the receiving framer, detection algorithms operate correctly in the presence of -3 a 10 bit error rate. The transmitting framer can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF, RED, or AIS, and FEBE upon detection of C-bit parity error. The outgoing framer may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers that are accessible by a generic microprocessor bus. Both T1 and E1 framing functionality are provided by the TEMUX. There are 28 T1 and 21 E1 framers. The T1 framers support both SF and ESF formats. Framers can be disabled to allow reception of unframed data. The E1 framers support FAS, NFAS, and CRC and CAS multiframe frame alignment and their respective framing bit errors. The framers support International/National bit extraction, distant alarms. Generate interrupts to signal a change in monitor bits or events, and on the basis of frames and multiframe. After reset, The TEMUX defaults to 28 T1 framers multiplexed into the M13 multiplexer using the DS3 M23 multiplex format. However some configuration is necessary for proper operation. The framers provide jitter attenuator for both directions using internal FIFOs and a jitter attenuated clock and reference clock XCLK (37.056MHz for T1 and 49.152MHz for E1). Refer to the TEMUX datasheet [11] for further details.
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3.6
FREEDM-32P672 The Frame Engine and Datalink Manager (FREEDM) is a family of advanced data link layer processors that is suitable for applications such as PPP interfaces for routers, TDM switches, Frame Relay interfaces for ATM or Frame Relay switches and multiplexers, internet access equipment, and Packet-based DSLAM equipment. FREEDM-32P672 implements HDLC frame processing and PCI Bus memory management functions for a maximum of 672 bi-directional channels. The FREEDM-32P672 may be configured to support 32 physical links for HMVIP, channelized T1/J1/E1, or unchannelized traffic. For channelized T1/J1/E1 links, the FREEDM-32P672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1, J1, or E1 links. Time-slots are determined using the gapped clock method. The channel assignment supports up to a maximum of 24 concatenated time-slots for T1/J1 and 31 for E1 link. For unchannelized links, it processes up to 32 bi-directional HDLC channels within 32 independently timed links. The aggregate bandwidth of the unchannelized links must no exceed 65.536 Mbs in either direction. Mixing of up to 32 channelized T1/J1/E1, unchannelized and H-MVIP links is supported; the number of channels in each direction is limited to 672 and the aggregate instantaneous clock rate over all 32 links is limited to 64MHz. In the receive direction, the FREEDM-32P672 performs channel assignment and packet extraction and validation. For each HDLC channel, the receive HDLC processor performs flag sequence detection, bit de-stuffing, and CRC-CCITT or CRC-32 verification. The resulting packet data is placed into the internal 32 Kbytes partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into the host packet memory. In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each HDLC channel, it DMA's partial packets across the PCI bus and into the partial packet buffer. The partial packets are read out of the packet buffer and a frame check sequence is optionally calculated and inserted at the end of each packet. The HDLC processor performs Flag insertion, bit stuffing, and CRC (CRC-32 or CRC-CCITT). DMA controllers are provided for both directions. They are responsible for transferring data into the host memory from the partial packet buffer and vice-
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versa. The capacity of partial packet buffer is 32 Kbytes, which is divided into 16 byte blocks. On the system side, the FREEDM-32P672 provides a 66MHz, 32-bit PCI 2.1 compliant bus interface. All transfers that occur between the FREEDM-32P672 and the host are done through data structures (ex. Receive Packet Descriptors (RPDs), reference queues) that are resident in the host memory. Since in this design the FREEDM-32P672 is interfaced with the TEMUX, only 28 links out of its 32 are used. Refer to the FREEDM-32P672 datasheet [12] for further details. 3.7 PCI-PCI Bridge Intel provides the PCI to PCI Bridge, PCI21152. It is fully compliant with PCI Local Bus Specification 2.1 and PCI-PCI Bridge Specification 1.1. It is a transparent device; i.e. it requires no special driver software to bridge one PCI bus to another. However, it does require initialization code to set up its configuration space and allocate memory space on the Secondary bus. The PCI21152 operates at 33MHz and has a standard PCI interface on the Primary bus side. On the Secondary bus side, it supports 4 PCI devices. It is also capable of arbitrating 4 devices on the Secondary side. It is also 3.3V and 5V tolerant. For configuration of the device, there are two types of transactions. Type 0 transactions are when the intended target resides on the same PCI bus as the initiator; Type 1 transactions are issued when the intended target resides on another PCI bus. The PCI21152 configuration space (Table 3) is accessed only by the Primary interface via a Type 0 configuration transaction. Only the PCI-PCI bridge responds to Type 1 transactions, which then are translated into Type 0 transactions for an intended device on the Secondary bus. In Type 1 transactions, a device number is specified to aid the PCI21152 in asserting a unique IDSEL signal on the Secondary bus. The Type 1 configuration format uses a 5-bit field at bits <15:11> in the address as a device number. A device number in Type 1 format is translated by the PCI21152 into an IDSEL line for Type 0 transactions on the target interface. It uses s_ad<31..16> as secondary IDSEL lines. There is a certain mapping that the device uses for translation of a device number to a s_ad pins. In this design, the FREEDM-32P672 is device #4 and the PCI9054 is device #8. Refer to the
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datasheet [4] and specifications [7] and [8] for more details, such as interrupt binding for expansion cards. Table 3
31
- PCI 21152 Configuration Space (main registers)
16 15 00
Device ID Status Reserved Class Code Header Type ... Secondary Latency Subordinate Bus Timer Number Secondary Status Memory Limit Address ... Bridge Control Arbiter Control ... Reserved p_serr_I Status ...
Vendor ID Command Primary Latency Timer Revision ID Cache Line Size
00h 04h 08 0Ch 18h 1Ch 20h 3Ch 40h 68h
Secondary Bus Primary Bus Number Number I/O Limit Address I/O Base Address Memory Base Address Interrupt Pin Diagnostic Control Reserved Chip Control
Secondary Clock Control
Arbitration for the Primary bus is done externally; i.e. by the host. The PCI21152 must arbitrate for the devices on the Secondary bus. Arbitration is performed for use of the Secondary bus when forwarding downstream (Secondary to Primary) transactions. The Secondary bus arbiter is internal and is enabled by having the s_cfn_i pin pulled low. In this design, only two devices will be arbitrated, namely the FREEDM-32P672 and the PCI9054 Local-PCI bridge. The FREEDM-32P672 needs to have both master and target capability, but the PCI9054 needs only to be a target. FREEDM-32P672 should be configured as a high priority group member. There is a Primary interface reset signal, p_rst_i, which is an input signal from the Primary bus. When a reset signal is received from the Primary bus, it is forwarded to all the devices residing on the Secondary bus via the output signal on the Secondary side, s_rst_i. Data throughput analysis of the FREEDM-32P672 operating in conjunction with the PCI-PCI Bridge has not been conducted. Detailed software configuration of the PCI21152 is highly dependent on the host and is beyond the scope of this reference design. Rather, detailed hardware implementation is the intended goal of this document. Please refer to the PCI21152 datasheet [4] for more details on configuring the Configuration register in Table 3, PCI Bus operations, addressing, arbitration, power management, ordering rules, and parity errors handling.
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3.8
PCI Bus Interface to the Host Processor and Packet Memory The FREEDM-32P672 is configured, controlled and monitored across the PCI bus interface by a host processor and packet memory (RAM). The GPIC subblock provides a 32-bit Master and Target interface core that contains all the required control functions for full PCI Bus 2.1 Compliance. The GPIC supports up to 66MHz and is also backward compatible with 33MHz and will operate at 33MHz when connected to a 33MHz PCI bus. During a bus transaction, the FREEDM-32P672 device may act as the bus master in accessing the packet memory, or the host processor may act as the bus master in accessing the FREEDM-32P672 registers. The data structures shown in Figure 5 are required to interface one FREEDM32P672 to the PCI bus. In this figure, PCI addresses are 32-bit physical addresses, which can be observed at the address pins of the PCI bus interface.
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Figure 5
- PCI Address Map
0 PCI ADDRESS MAP
Data Buffers
Tx Queue Base
Rx Queue Base
Transmit Descriptor Queues Receive Descriptor Queues Transmit Descriptor Table Rx Packet Descriptor Table
RAM Addresses (Packet Memory)
Tx Descriptor Table Base
Rx Descriptor Table Base
CBI Register Base Address
Normal Mode Register Space
FREEDM Addresses (4KB)
4GB
When multiple FREEDM-32P672's are attached to the bus each FREEDM32P672 must have a unique set of the following data structures: Transmit Queue Space, Receive Queue Space, Transmit Descriptor Table, Receive Descriptor Table, and CBI Registers Space. The data structures within packet memory are accessed by software running on the host processor or by the FREEDM-32P672. The software specifies the
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location of these data structures by writing base addresses into the appropriate FREEDM-32P672 registers, before activating the FREEDM-32P672. The data Buffers are filled with the data received by the FREEDM-32P672, or contain transmit data, which is read by the FREEDM-32P672. The descriptor tables and the queues are required to manage these buffers. To manage and control the FREEDM-32P672 device, software running on the host processor accesses the Normal Mode Register space. The CBI Registers Base Address is used as the base address for registers that control the PCI interface. These registers are located in the FREEDM-32P672 and are accessed by the CBI bus interface. The PCI Configuration Space does not reside in the PCI address map, but it is a requirement for all PCI devices. The Configuration Space is a block of 256 contiguous bytes that reside in the PCI device (the FREEDM-32P672 in this case), and is accessed by the host processor in a PCI bus Configuration Read (or Write) transaction, rather than a Memory Read (or Write) transaction. Access to this configuration space is system specific and a thorough description of it can be found in the PCI specification [7]. A description of the software can be found in the application note [14]. Note: Special care must be taken when configuring the software between the FREEDM-32P672 and the PCI21152. 3.9 Timing Block There are four oscillator sources on the board. The TEMUX requires a Transmit Input Clock (TICLK) of 44.736MHz for the transmit direction and a Crystal Clock (XCLK) of 37.056MHz (T1) or 49.152MHz (E1) for timing many of the T1/E1 sub-blocks. It also requires a Common Transmit Clock (CTCLK) of 12.352/16.384MHz (T1/E1) for operation in Master modes. To support both T1 and E1, the corresponding oscillators (above) can be easily interchanged using socket-packaged oscillators. An 8MHz clock is also need for the Local bus, and it is used by the CPLD and PCI9054.
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3.10
Power Block The majority of devices on the board will operate of the +3.3V rail, however, the TEMUX and FREEDM-32P672 devices require +3.3V for the I/O pads and +2.5V for the core logic. In this design, a Universal PCI back plane connector will provide a 5V supply, which is regulated to provide 2.5V and 3.3V power supplies. If designed otherwise, the 3.3V can also be used instead of the 5V to supply the 3.3V devices and regulate for the 2.5V source. The DS3 LIU, PCI-PCI Bridge, Local-PCI Bridge, SEEP, CPLD, logic gates, buffers, and oscillators will operate at +3.3V.
3.11
Front Panel Front panel LEDs will be used to indicate status of the power supplies. Reset circuitry is implemented using a voltage monitor and manual reset device. A reset command propagates throughout the whole board on either of the following conditions. The first condition is if a manual reset was performed; i.e. reset button was activated (low). The second condition is if the monitored voltage falls beyond a certain threshold of its intended value. The latter condition protects against data corruption caused by power supply instability. Software reset control is also facilitated in the design using a standard PCI reset signal which is received through the PCI connector and passed on to all devices via the PCI-PCI Bridge. Moreover, individual devices can also be reset under software control, i.e. using internal control register.
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4
DESIGN ISSUES The following sections describe detailed design considerations of the reference design.
4.1
DS3 LIU
4.1.1 TDK78P2241 3.3V versus 5V A new feature has been added in the 3.3V device, the LIN are internally forced low when /LOS indicates low. This is to guard against the received signal from being lower than a certain threshold, which would otherwise cause signal corruption. According to characterization results of the 3.3V device, the micro strips for the LOUT and LIN pins should be less than 12 inches (approximately) to avoid attributed signal degradation. 4.1.2 Power Supply De-coupling capacitors are used on the power to reduce the effects of noise from the power supply. 4.1.3 Transformers A 1:1 transformer is coupled to the receiver and a 2:1 transformer is coupled to the transmitter. 4.1.4 Termination Resistors A 75 resistor must terminate the AMI incoming line. A 301 resistor must terminate the AMI outgoing line. 4.2 TEMUX
4.2.1 Power Supply The TEMUX is operated at 2.5V for the core logic and at 3.3V for the I/O pads. The 5V is used for generating the 2.5V and 3.3V supplies. The 3.3V supply should be powered up before and powered down after the 2.5V.
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4.2.2 De-coupling Capacitors of 0.01 F are used to achieve de-coupling of power pins on the device. 4.3 FREEDM-32P672
4.3.1 Power Supply The FREEDM-32P672 is operated at 2.5V for the core logic and at 3.3V for the I/O pads. The 5V is used for generating the 2.5V and 3.3V supplies. The 3.3V supply should be powered up before and powered down after the 2.5V. 4.3.2 Timing The FREEDM-32P672 core logic can be operated at clock of 25 to 40MHz, via the SYSCLK pin. In this design a buffered version of the PCI bus clock is used and it has a value of 33MHz. 4.3.3 De-coupling Capacitors of 0.01 F are used to achieve de-coupling of power pins on the device. 4.4 PCI 9054
4.4.1 Power Supply The PCI9054 core logic is operated at 3.3V. 4.4.2 CPLD A CPLD is used to house some glue logic, which is required to interface the PCI9054 to the TEMUX. The PCI9054 is a master and the TEMUX is a slave. The CPLD is implemented to meet the TEMUX micro interface timing requirements (refer to the datasheet [11] for more timing details). Read and Write timing diagrams are provided to illustrate the implementation of the CPLD. The clock provided to the CPLD is 8MHz, i.e. with a 125ns period. Please refer to the VHDL code segment in Appendix C: VHDL Code for Glue Logic. Assigning pin numbers to signals can easily be specified in VHDL code, however, this is not provided in the code segment given.
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Figure 6 and Figure 7 show the timing requirements of the TEMUX for Read and Write operation, respectively. Figure 6 - TEMUX Read Timing Diagram
LCLK_CPLD (8 MHz)
INPUT
HOLD-9054
ADSB_9054
W_RB_9054
OUTPUT
READYB_9054
RDB_TEMUX & CSB_TEMUX
62.5 ns 10 ns min.
LOCAL BUS
A_TEMUX
D_TEMUX
Provided Time
125 ns
70 ns max
Required Time
80 ns max
READ
Figure 7
- TEMUX Write Timing Diagram
LCLK_CPLD (8 MHz)
INPUT
HOLD-9054
ADSB_9054
W_RB_9054
OUTPUT
READYB_9054
62.5 ns
WRB_TEMUX & CSB_TEMUX
40 ns min
62.5 ns 10 ns min.
LOCAL BUS
A_TEMUX
D_TEMUX
Provided Time Required Time
62.5 ns 20 ns min
62.5 ns 5 ns min
WRITE
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4.5
PCI 21152
4.5.1 Power Supply The PCI21152 core logic is operated at 3.3V. 4.5.2 Timing This device has 2 clock input signals (s_clk and p_clk) and 5 clock output signals (s_clk_o<4:0>). Input p_clk receives the Primary PCI bus clock signal. The output clocks s_clk_o<4:0> are for the Secondary bus devices, one of which is fed back into the s_clk input. Two Secondary devices require a clock signal each, that is, the FREEDM-32P672 and the PCI9054 Bridge. Hence, in total only 3 of the output s_clk_o are used. The Primary and Secondary clocks must be synchronized with maximum skew of 7 ns. The skew between the Primary input (p_clk) and Secondary outputs (s_clk_o<4:0>) is 5 ns. Therefore, only 2 ns is allowed for Secondary clock etch returning to the s_clk input. Each Secondary clock output is limited to one load. It is recommended to use equivalent amount of etch on the board for all Secondary clocks, to minimize skew between them. It is also recommended to disable unused Secondary clock outputs to reduce power dissipation and noise in the system. They can be disabled using the Secondary clock control register in configuration space. 4.6 Timing Distribution There are 4 timing sources in this design. Three of which are required by the TEMUX and are generated by on-board oscillators. These oscillators are powered at 3.3V. The fourth source is the PCI bus clock. It is obtained from the PCI connector and fed into the PCI-to-PCI bridge Primary clock input signal. Clocks that are needed by the FREEDM-32P672 and the Local-to-PCI bridge are distributed by the PCIto-PCI bridge as explained in the PCI21152 Timing section. 4.7 Power Requirements The parts and their maximum power requirements for the FREEDM-32P672 with DS3 LIU reference design are listed in Table 4.
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Table 4
Voltage 5V 5V Total 3.3V
- Component Power Consumption
Components LED Quantity 1 Current (mA) 10 Power (mW) 50 50 315 1200 1000 50 1000 500 304 33 4400 1300 1350 25 2675 7127
TDK78P2241 Intel PCI21152 PLX PCI9054 Xilinx CPLD Pericom 8-bit Driver Fairchild Quad AND Oscillators LED TEMUX FREEDM-32P672 LED TOTAL
1 1 1 1 1 1 4 1 1 1 1 2 Averaged value.
95 1 15 2 23 10 10 -
3.3V Total 2.5V 2.5 Total
1 Estimated value as it highly depends on the design.
Values represent the worst case.
4.8
Connectors
4.8.1 JTAG Port The PCI connector provides the JTAG pins. Only the TEMUX and FREEDM32P672 support JTAG. The PCI9054 and PCI21152 support NAND-TREE testing, please refer to their respective datasheets for details. 4.8.2 PCI Connector A universal PCI connector is used in this design. Positions A50/B50, A51/B51, A12/B12, and A13/B13 of the universal PCI connector are used for the keying mechanism. PCI implements a keying mechanism to differentiate 5V from 3.3V signaling. The keying mechanism is designed to prevent a board built with one buffer technology (3.3V or 5V) from being inserted into a system designed for the other buffer technology (5V or 3.3V, respectively). A universal PCI connector is meant for an environment that can support either 5V or 3.3V, hence allowing for more flexibility. For this design however, the back-plane signaling environment must provide 5V, since the 5V source is used to regulate the 2.5V and 3.3V supplies.
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4.8.3 Headers One, two, and four pin headers are used with several of the devices on the board for the purpose of probing or device configuration. Refer to the schematic details.
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5 5.1
SOFTWARE INTERFACES General Overview Although, in this section some software issues are addressed, be advised that detailed software configuration is highly dependent on the environment and it is beyond the scope of this reference design. The intended goal of this document is to illustrate the hardware interfacing of the devices to achieve a DS3 application.
5.2
TEMUX Configuration and monitoring of the TEMUX can be accomplished by the host processor via the PCI9054 bridge, PCI21152, and the PCI connector. Normal mode registers are used to configure and monitor the operation of the TEMUX. Normal mode registers are selected when TRS (A [13]) is low. Refer to the TEMUX register description document [13] for more details. Also refer to the TEMUX datasheet [11] for further clarification. The interface from the PCI9054 bridge must provide an 8-bit bi-directional data bus and 14-bit address bus. Signal interfaces required are Interrupt (INTB), Chip Select (CSB), Read Enable (RDB), Write Strobe (WRB), and Reset (RSTB). Most of which are facilitated by the CPLD from a different set of signals that are provided by the PCI9054. Address Latch Enable (ALE) pin is pulled high to disable multiplexing of data and address pins.
5.3
FREEDM-32P672 The FREEDM-32P672 is configured and monitored across the PCI bus interface by a host processor and packet memory (RAM). There are 2 types of registers: PCI Host Accessible registers and PCI Configuration registers. Description and handling of both PCI register types is detailed in the FREEDM-32P672 datasheet [12] and the application note [14].
5.4
FREEDM-32P672 PCI Configuration Configuration of the interface is done by the GPIC target machine sub-block in the FREEDM-32P672. It provides the PCI Configuration registers. The configuration registers can only be accessed through the PCI Host interface. These registers can only be accessed when the GPIC is a target and a configuration cycle is in progress as indicated using the IDSEL input.
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The CBI bus interface provides access to the CBI address space of the FREEDM-32P672 blocks. The CBI address space is set by the associated BAR in the PCI Configuration registers. Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of the status of the byte enables, as long as at least one byte enable is asserted. A read command with all byte enables negated will be ignored. Refer to the datasheet [12] for more details. 5.5 PCI 9054 Configuration Table 5 specifies the values that should be programmed into the SEEP for configuring the address mapping. These values will be loaded into the PCI9054 registers on power-up. Please refer to the PCI9054 datasheet [9] for further configuration details. Before programming the SEEP with the values below, the SEEP should be initialized with known values (such as 0x0). This is to ensure safety when overwriting other register in the PCI9054 that are not indicated here. Also, many of the registers (not listed below) in the PCI9054 take on default values after reset, changing (overwriting) these values should be avoided. The values listed below are loaded in sequence of the SEEP offset, with the MSB loaded first. Refer to the PCI9054 datasheet [9] for more information.
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Table 5
Register PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] PCIIPR[7:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] BIGEND[7:0] LBRD0[31:16] LBRD0[31:16]
- PCI 9054 Configuration Registers Values
SEEP Offset 0x00 0x02 0x04 0x06 0x0A 0x14 0x16 0X18 0X1 A 0x22 0x2C 0x2E Description Device ID Vendor ID Class Code Class Code/Revision Interrupt Pin/Interrupt Line Routing 1 MSW of Range for PCI-to-Local Address Space 0 1 LSW of Range for PCI-to-Local Address Space 0 MSW of Local Base Address (Re-map) for PCI-toLocal Address Space 0 2 LSW of Local Base Address (Re-map) for PCI-toLocal Address Space 0 LSW of local Bus Big/Little Endian Descriptor Register MSW of Bus Region Descriptors for PCI-to-Local Accesses LSW of Bus Region Descriptors for PCI-to-Local Accesses
2
Value 0x9054 0x10B5 0x0680 0x0000 0x0001 0xFFFF 0xC000 0x0000 0x0001 0x0005 0x0000 0x0340
1 These values indicate to the PCI9054 a 14-bit address range to satisfy the TEMUX requirement. The values shown are actually the inverse of the address range - this representation is required by the PCI9054. Address Space 0. The lowest bit must be set to enable PCI host access to Local
Note that in this design there is only one device, TEMUX, on the Local bus, consequently only one address space is required. Hence Address Space 0 is being used. Other address space can be configured if more devices are present on the Local bus. Referring to Figure 4, the PCI Base Address is not included in Table 5 and is configured by the PCI initialization software. Configuration registers can be written to via the SEEP or the Local or PCI bus. 5.6 PCI 21152 Configuration The host initialization software is required to provide the following functions during the initialization process: * * * * Assigning PCI bus numbers Allocating address ranges Writing IRQ numbers into each device PCI bus numbers
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To initialize the PCI21152 so that memory, I/O, and configuration transaction can be forwarded, use Table 6 to write to the bridge configuration registers. Numerical values are not provided in the table because it is dependent on the system. If this card is residing on a host system, which is behind another PCI Bridge then the numbering of PCI buses and bridges will differ accordingly. Refer to the PCI21152 datasheet [4] and the PCI-to-PCI Bridge Architecture Specification Rev. 1.1 [8]. Table 6
Register Name Subordinate/ Secondary/Primary bus numbers Secondary status/ I/O limit address/ I/O base address Memory limit/ Memory base
- PCI21152 Initialization of Configuration Registers
Configuration Space Offset in PCI21152 18h Value Notes XX = subordinate bus number = YY YY = Secondary bus number ZZ = Primary bus number Clear status bits. X = I/O limit address bits <15:12> Y = I/O base address bits <15:12> XXX = nonprefetchable memory limit address <31:20> YYY = nonprefetchable memory base address <31:20> To disable this range, write 0000FFFFh. XXX = prefetchable memory limit address <31:20> YYY = prefetchable memory base address <31:20> To disable this range, write 0000FFFFh. X = 0 (no ISA bus in system) Clear status bits. Turn on I/O enable for downstream I/O. Turn on memory enable for downstream memory. Turn on master enable for upstream memory and I/O. Write this register last.
00XXYYZZh
1Ch
FFFFX0Y0h
20h
XXX0YYY0h
PF memory limit/ PF memory base Bridge control
24h 3Ch
XXX0YYY0h 000X0000h
Primary status/ Command
04h
FFFF0007h
The PCI21152 has a set of Memory Mapped (MM) I/O base and limit address registers (Table 7) in configuration space that define MM I/O address range for I/O address forwarding. It supports 32-bit MM I/O addressing, which allows MM I/O downstream addressing to be mapped anywhere in a 4 GB MM I/O address space. MM I/O transactions with addresses that fall inside the range are forwarded downstream. MM I/O transactions with addresses that fall outside this range are forwarded upstream.
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Table 7
Register Name --Memory Base Address Memory Limit Address
1 Assumed value
- PCI21152 Memory-Mapped I/O Space Registers
Field Width 20 20 16 16 Value 0 0 Z15..Z4 0000h Z15..Z4 0000h
2
Configuration Space Offset in PCI21152 --20h 22h
Representation Memory_address <19:0> 0 for MM I/O Base Address; aligns address to 1MB boundary 1 Memory_address <19:0> F FFFFh for MM I/O Limit Address; aligns address to 1MB boundary Z15..Z4 = memory address <31:20> for Base Address Z15..Z4 = memory address <31:20> for Base Address
1
2
2 The bottom 4 bits are hardwired to a hexadecimal value of 0000.
To enable downstream forwarding of MM I/O transactions, the MM I/O enable bit must be set in the command register; similarly for upstream forwarding of MM I/O transactions, the master enable bit must be set in the command register. These configurations must be done after the base and Limit address configuration (above) and while both buses are idle. Memory-Mapped (MM) I/O transactions are needed by the FREEDM-32P672 device. Similar to the MM I/O addresses, the I/O enable bit and master bit must be set in the command register to enable downstream and upstream of I/O transactions, respectively. The I/O Base and Limit registers also define a range that the PCI21152 uses to determine when to forward I/O commands. Transactions are forwarded downstream if the address falls in the range and upstream outside the range. Table 8 lists the address range. This address range supports 32-bit addressing only. Address range configuration must be done before enabling the bits.
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Table 8
Register Name --I/O Base Address I/O Limit Address I/O Base Address Upper 16 bits I/O Limit Address Upper 16 bits
1 Assumed value is supported.
- PCI21152 I/O Address Space Registers
Field Width 12 12 8 8 16 Value 0 0 ZZZZ 1111h ZZZZ 1111h Z15..Z0
2 2
Configuration Space Offset in PCI21152 --1Ch 1Dh 30h
Representation AD<11:0> 0 for Base Address; aligns address to 4KB boundary 1 AD<11:0> FFF for Limit Address; aligns address to 4KB boundary ZZZZ = AD<15:12> of I/O Base Address ZZZZ = AD<15:12> of I/O Limit Address Z0..Z15 = AD<31:16> of I/O Base Address Z0..Z15 = AD<31:16> of I/O Limit Address
1
32h
16
Z15..Z0
2 The bottom 4 bits are read only and have a hexadecimal value of 1111 to indicate that 32-bit I/O addressing
Similarly, the space address registers in the table above are not provided with numerical values, because it is dependent on the host system. Please refer to the PCI21152 datasheet [4] and specifications [7] and [8] for more details.
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6 6.1
COMPONENT SELECTION PCI-PCI Bridges * Intel PCI21152 is the best suitable option for this design because the vendor has other current devices (already developed) in its family, which allows for potential of upgrading; for example support for 66MHz and 64bit. To further improve this design, Intel's PCI21154 can be used to allow for 66MHz bus. At this clock frequency the FREEDM-32P672 is utilized to its fullest potential. However, all other devices on the secondary bus must also operate at 66MHz. The limiting device in this design would be PLX's PCI9054, which operates at a maximum PCI bus frequency of 33MHz. PLX's PCI9610 would be ideal as it operates at 66MHz, however it is not available as of this date. HiNT HB1 is another device that is suitable. However, this product is the first in its line, so potential of upgrading is not as vast. TI PCI 2031 is also sufficient for the functionality needed. However, it supports PCI-PCI bridge specification ver. 1.0 and not 1.1, which takes into consideration delayed transactions. Also, It is the only active device in its line - again, limited upgrade potential.
* *
6.2
Oscillator The on-board oscillators provide timing references. The stability figure of an oscillator should include any variation due to calibration, temperature, voltage, load, aging, shock, and vibration, and is specified over the lifetime of the oscillator. The TEMUX requires three oscillators. They should have stability of 32ppm or better and 50% duty cycle. Either CMOS or TTL oscillator can be used. The following are some vendors that provide these oscillators: Table 9
MMD Ecliptek Champion
- Oscillator Vendors
Vendor 32ppm or better Yes Yes Yes
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
6.3
De-coupling and Bypass Capacitors In this design, power pins de-coupling is achieved by 0.01 F and 0.1 F capacitors. Tantalum capacitors of 22 F are used for bulk de-coupling.
6.4
Resistors Resistors used for terminating the DS3 LIU should have tolerance of 1%. Other terminating, pull-up, and pull-down resistors can be of 5% tolerance.
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
7
GLOSSARY AIS AMI ATM BAR CAS CBI COFA ESF EXZ FAS FEAC FEBE FERF GPIC HDLC IRQ LOS NFAS OOF RAI SBI SF Alarm Indication Signal Alternate Mark Inversion Asynchronous Transfer Mode Base Address Register Channel Associated Signaling Control Block Interface Change of Frame Alignment Extended Superframe Excessive Zero Frame Alignment Signal Far End Alarm Control Far End Block Failure Far End Receive Failure General Purpose Peripheral Component Interconnect Controller (Sub block in the FREEDM-32P672) High-level Data Link Control (protocol) Interrupt Request Loss of Signal No Frame Alignment Signal Out of Frame Remote Alarm Indication Scalable Bandwidth Interconnect Standard Superframe
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
8
REFERENCES 1. Fairchild Semiconductor Corp., "NM93CS56 (MICROWIRETM Bus Interface) 2K-bit Serial EEPROM with Data Protect and Sequential Read." (datasheet) March 1999. 2. Intel Corp., "21152 PCI-to-PCI Bridge Configuration Application Note." July 1998. 3. Intel Corp., "21152 PCI-to-PCI Bridge Hardware Implementation Application Note." March 1999. 4. Intel Corp., "21152 PCI-to-PCI Bridge Preliminary Datasheet." October 1998. 5. Maxim Integrated Products, "4-Pin uP Voltage Monitors with Manual Reset Input." (datasheet) February 1998 Rev. 2. 6. MindSahre Inc., "PCI System Architecture." Addison Wesley Longman Inc., 1999, 4th ed. 7. PCI Special Interest Group, "PCI Local Bus Specification Rev. 2.2." December 1998. 8. PCI Special Interest Group, "PCI-to-PCI Bridge Architecture Specification Rev. 1.1." December 1998. 9. PLX Technology Inc., "PCI 9054 Data Book." November 1998, ver. 1.0. 10. PMC-Sierra Inc., PMC-950946, "Interfacing the DSMX to the SSI 78P7200." September 1995, Issue 1. 11. PMC-Sierra Inc., PMC-981125, "TEMUX High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer Datasheet." June 1999 Issue 4. 12. PMC-Sierra Inc., PMC-990262, "FREEDM-32P672 - 32 Link, 672 Channel Frame Engine and Datalink Manager Datasheet." May 1999, Issue 2. 13. PMC-Sierra Inc., PMC-990495, "TEMUX High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer Register Descriptions." July 1999 Issue 2. 14. PMC-Sierra Inc., PMC-990545, "Frame Engine and Datalink Manager 32P672 Programmer's Guide." June 1999, Issue 2.
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
15. TDK Semiconductor Corp., "Advanced Information 78P2241 E3/DS3/STS-1 Transceiver." September 1999.
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9
DISCLAIMER This document is a paper reference design, and as such, has not been built or tested as of this date.
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
10
APPENDIX A: SCHEMATIC This schematic is comprised of 9 pages as follows: Sheet 1: Root Drawing This sheet provides a block diagram of the interface signals between blocks. The transmit/receive signals start at the T3 Line Interface and propagate to the PCIPCI Bridge block. * The Secondary PCI bus connecting the FREEDM-32P672, Local-PCI-Bridge, and PCI-PCI-Bridge blocks is comprised of the standard PCI bus signals. In addition, interrupt signals are forwarded from the FREEDM-32P672 and Local-PCI-Bridge blocks to the Primary PCI Bus via the PCI-PCI-Bridge block. Also, secondary clocks are distributed by the PCI-PCI-Bridge block from the primary PCI clock to the FREEDM-32P672 and the Local-PCI-Bridge blocks. The FREEDM-32P672 and the TEMUX are programmed by the host processor via the PCI bridges. The TEMUX is not a PCI device and thus it requires a PCI bride, Local-PCIBridge block, to the interface to the PCI bus and ultimately the host processor. The Oscillator block provides timing for the TEMUX and the Local-PCI-Bridge blocks. Clock trace length should be kept to a minimum to reduce adverse affects. The secondary clock traces should have similar length to reduce skew. The reset signal from the Power block is routed to the PCI-PCI Bridge, and is then distributed via the secondary PCI bus to all other devices. The system is reset via the Primary PCI bus, whenever the host is reset, or when the reset switch is active. A JTAG chain is extended from PCI connector to connect the FREEDM32P672 and TEMUX blocks and the CPLD in the Local-PCI-Bridge block. 75 signals impedance is maintained throughout the whole design.
* *
*
*
* *
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
Sheet 2: Line Interface Unit This sheet provides an interface to the T3 port using the TDK78P2241 DS-3 Line Interface Transceiver. Resistors and capacitors are connected as outlined in the manufacturer's datasheet for the device. * LPBK header allows the user to manually enable/disable Loop-back. When /LPBK is tied low, analog (AMI) loop-back is selected; when float, Digital loopback is selected; when high, no loop-back is selected. For typical operation, the jumper should be tied high. ICKP header allows the user to manually invert the RCLK and TCLK. When ICKP is tied low, both clocks are normal; when float, both are inverted; when high, RCLK is normal and TCLK is inverted. LBO head allows the user to setup the device appropriately according to the cable length. Logic low for 225ft of cable or logic high for < 225ft of cable. A probe point is provided by J7 for monitoring the LIN for signal loss. The wires TCLK_LIU, TPOS, TNEG, RCLK_LIU, RPOS, and RNEG are provided in 75 controlled impedance traces. The transformers used should have 3% tolerance. The Bantam connectors are connected to chassis ground for better isolation. Three pins (7, 17, 26) are connected to VCC, each of which requires decoupling capacitors of 0.1 F and 4.7 F to stabilize any variations in the power supply.
*
* * * * * *
Sheet 3, 4: TEMUX EGRESS (1/2) and TEMUX INGRESS (2/2) These sheets provide the TEMUX. T1 functionality has been assumed and hence implemented in this design. The TEMUX provides the DS3 multiplexing/demultiplexing and the T1/E1 framing. * * The TEMUX operates at 2.5V for the core logic and 3.3V for the I/O pads. CTCLK is 12.352MHz since T1 is assumed. CTCLK, TICLK (44.736MHz), XCLK (37.056MHz), TCLK<27..0>, and RCLK<27..0> are all provided via 75 controlled impedance traces.
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
*
Unused input pins are disabled - either by pull up or down resistors of 4.7 K or 330 , respectively. Unused output pins are ignored. Since in this design, the TEMUX is connected serially with the FREEDM-32P672, it is operated in serial mode and unused pins are intended for other modes and interfaces that the TEMUX supports, such as SBI bus interface. The IFP<28..1> output signals are framing pulse signals intended for accompanying the Ingress data, but it is not needed by the FREEDM-32P672 in this design, since each signal has a corresponding clock signal. The micro interface is connected through the Local-PCI-Bridge and PCI-PCIBridge to the host processor. Termination resistors of 51 along with the internal resistance ( 22 ) of the device match trace impedance of 75 . Open drain pins such as interrupt pins are pulled up by 4.7 K resistors. Capacitors of 0.01 F are used on all power pins for de-coupling the power supply noise.
* * * *
Sheet 5: FREEDM-32P672 This sheet provides the frame relay HDLC processor. The FREEDM-32P672 (PM7380). * * * * * The FREEDM-32P672 has a standard PCI bus interface. The FREEDM-32P672 operates at 2.5V for the core logic and 3.3V for the I/O pads. The M66EN is set low for 33MHz PCI bus operation. It receives a 33MHz secondary clock from the PCI21152. The PCI1_IDSEL_FREEDM derived from PCI_AD<20> is fed into the IDSEL pin of the FREEDM-32P672 device. The PCI-PCI-Bridge, PCI21152, provides the PCI IDSEL signals for devices on the Secondary bus using selected address lines. PCI_AD<20> is understood as Device #4 by the PCI21152. It should be noted that PCI operations intended for the FREEDM-32P672 are routed via the PCI21152 using this device number along with the bus number. There are many other ways of selecting this device number - refer to the PCI21152 datasheet [4]. Unused input pins are disabled - either by pull up or down resistors of 4.7 K or 330 , respectively. Unused output pins are ignored. Since in this design,
*
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
the FREEDM-32P672 is used with the TEMUX only 28 pins are connected for the transmit/receive data signals. Also the FREEDM-32P672 and TEMUX are connected serially with corresponding data and clock signals, consequently the M-VIP interface (T/RMVCK<3..0>, T/RMV8FPC, T/RMV8DC, T/RFPB, T/RFP8B) is not used. The PMCTEST pin is disable to allow for normal operation. * * * * Headers J6, J8, J9, and J10 provide access to the Transmit and Receive Bit Error Rate Test Data and Clock signals. Termination resistors of 51 along with the internal resistance ( 22 ) of the device match trace impedance of 75 . Open drain pins such as interrupt pins are pulled up by 4.7 K resistors. Capacitors of 0.01 F are used on all power pins for de-coupling the power supply noise.
Sheet 6: Oscillator Block This sheet provides the timing for the TEMUX, PCI9054, and CPLD. * The TEMUX requires Transmit Input Clock (TICLK) of 44.736MHz for the transmit direction and Crystal Clock (XCLK) of 37.056MHz (T1) or 49.152MHz (E1) for timing many of the T1/E1 sub-blocks. It also requires Common Transmit Clock (CTCLK) of 12.352/16.384MHz (T1/E1) for operation in Master modes. To support both T1 and E1, the corresponding oscillators can be easily interchanged using socket-packaged oscillators. An 8MHz clock is also need for the Local bus, and it is used by the CPLD and PCI9054. The TEMUX oscillators should have stability of 32ppm or better and 50% duty cycle. Capacitors of 0.01 F and 0.1 F are used on all power pins for de-coupling the power supply noise.
* * * *
Sheet 7: Local To PCI Bridge & CPLD This sheet provides the Local to PCI bridge and glue logic to interface the TEMUX to the secondary PCI bus.
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
* * *
The PCI9054 has a standard PCI bus interface. The PCI21152 core logic operates at 3.3V. The PCI1_IDSEL_9054 derived from PCI_AD<24> is fed into the IDSEL pin of the PCI9054 device. The PCI-PCI-Bridge, PCI21152, provides the PCI IDSEL signals for devices on the Secondary bus using selected address lines. PCI_AD<24> is understood as Device #8 by the PCI21152. It should be noted that PCI operations intended for the PCI9054 are routed via the PCI21152 using this device number along with the bus number. There are many other ways of selecting this device number - refer to the PCI21152 datasheet [4]. It receives a 33MHz secondary clock signal (PCI9054_SCLK) from the PCI21152 for the PCI bus side and an 8MHz clock signal (LCLK_9054) for the Local side. Mode<1..0> pins are pulled low for C-Mode operation. To configure an 8-bit data bus, pins LBEB<1..0> are use as LA<1..0> and pins LBEB<3..2> are disabled. J11 is for accessibility to facilitate miscellaneous user I/O pins. The NM93CS56 is a SEEP device, used to load configuration data after reset. This device is dip socketed to allow for I/O data programming. Unused input pins are disabled - either by pull up or down resistors of 4.7 K or 330 , respectively. Unused output pins are ignored. The TEST pin is disabled to allow for normal operation. The BIGEND# pin is not used, rather software configuration of Big/Little Endian ordering is preferable. Signals HOLD, W_RB, READYB, and ADSB are used in the CPLD glue logic to interface to the TEMUX micro interface, which has the signals RDB_TEMUX, WRB_TEMUX, CSB_TEMUX, and RSTB_TEMUX. The INTB_TEMUX is just buffered and forwarded to LOC_INTB signal. It is passed through the CPLD for expandability purposes. Pins LHOLD and LHOLDA on the PCI9054 are connected since the PCI9054 is always the master of the Local bus. The CPLD is assumed to be socketed. However, JTAG programming is still possible via the J14 header. For normal JTAG testing short the header across and for CPLD programming use header pins (1, 3, 5, 7).
*
* * * * *
*
* * *
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
* *
Spare pins on the CPLD are connected to headers J12 and J13 for easier access. Each header is also connected to VDD 3.3V and GND. Pin assignment on the CPLD can be specified by VHDL code to match the schematic. However, this is not necessary as long as the CPLD pins are properly connected before layout. Open drain pins such as interrupt pins are pulled up by 4.7 K resistors. Capacitors of 0.01 F are used on all power pins for de-coupling the power supply noise.
* *
Sheet 8: PCI To PCI Bridge This sheet provides the PCI-PCI-Bridge and the PCI edge connector. * * * The PCI21152 has standard PCI signals on both, the Primary and Secondary sides. The S_CFN_I is pulled low to enable the internal arbiter for the Secondary bus. The Secondary clock signals, S_CLK<2..0>, should have similar etch length to minimize skew. The other secondary clocks are disabled by software and pins S_CLK<3..4> are ignored. The AND gate provides the reset function upon receiving an activation from the Power block or the PCI connector. The S_VIO and P_VIO pins on the PCI21152 are both connected to 3.3V to configure both the Primary and Secondary sides to 3.3V signaling. Unused input pins on the PCI21152 are disabled - either by pull up or down resistors of 4.7 K or 330 , respectively. Unused output pins are ignored. Only S_REQ_I<0> and S_GNT_I<0> are used by the FREEDM-32P672, since it needs to be the master of the PCI Primary. The rest of the signals are disabled. The 3.3V pins are connected together but are not used; instead, the 5V supply is used since the commonly available motherboard provides 5V supply. Pins VI/O are dynamic in a Universal PCI connector, i.e. they can be 3.3V or 5V depending on the signaling environment and should be unconnected. For
* * *
*
*
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
this design to work properly, 5V supply must be available in the back-plane signaling environment. * Both PRSNT1# and PRSNT2# should be grounded on the PCI connector to indicate a 7.5 W total power consumption by the card. For 15 W, PRSNT1# remains floating. Termination resistors of 51 along with the internal resistance ( 22 ) of the device match trace impedance of 75 . Open drain pins such as interrupt pins are pulled up by 4.7 resistors. Capacitors of 0.01 F are used on all power pins for de-coupling the power supply noise.
* * *
Sheet 9: Power Block This sheet provides the 3.3V and the 2.5V power supplies for the reference design, as well as the reset circuitry. * The 5V supply is received from the PCI connector. The 5V supply is regulated to provide the 2.5V and 3.3V supplies. The 2.5V is regulated by the LT11182.5 and the 3.3V by the LT1117-3.3. 3A fuse is used for reducing the risk of short circuit the power supply. LEDs are used to indicate the status of the power supplies. Resistors are used to limit the amount of current that flows into the LEDs to approximately 10A. 22 F tantalum capacitors are used for bulk de-coupling. For the voltage regulator de-coupling, 22 F and 10 F are used as recommended by the manufacturer. It is also recommended that a 0.1 F ceramic capacitor be paralleled with the output of the LT1118 to maintain quick settling time. The reset circuit VCC pin is not de-coupled so that it can sense any variations in the voltage. Reset circuitry is implemented using voltage monitor MAX811 from Maxim. A reset command propagates throughout all devices if a manual reset was performed; i.e. reset button was activated (low) or if the monitored voltage falls beyond a certain threshold. The threshold for MAX811S (3.3V monitor) is
* *
* *
* *
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
min. 2.88V at +25C. Also, MAX811S provides the de-bouncing for the reset button.
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42
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ROOT DRAWING
H TEMUX TICLK XCLK CTCLK RCLK_LIU RPOS_LIU RNEG_LIU TPOS_TEMUX TNEG_TEMUX TCLK_TEMUX G PAGE 2 A_TEMUX<13..0> D_TEMUX<7..0> RDB_TEMUX WRB_TEMUX CSB_TEMUX INTB_TEMUX RSTB_TEUMX RCLK_LIU RPOS_LIU RNEG_LIU TPOS_TEMUX TNEG_TEMUX TCLK_TEMUX RCLK_LIU RPOS_LIU RNEG_LIU TPOS_TEMUX TNEG_TEMUX TCLK_TEMUX TD<27..0> TCLK<27..0> RD<27..0> RCLK<27..0> A_TEMUX<13..0> D_TEMUX<7..0> RDB_TEMUX WRB_TEMUX CSB_TEMUX INTB_TEMUX RSTB_TEMUX TICLK XCLK CTCLK OSCILLATORS_BLOCK TICLK XCLK CTCLK LCLK
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T3 LINE INTERFACE
TD<27..0>
RD<27..0> G
PAGE 6 TDO_TEMUX TRSTB_PCI TMS_PCI TCK_PCI TDO_FREEDM
FREEDM_32P672
PAGE 3,4
F TCLK<27..0>
TD<27..0> TCLK<27..0> RD<27..0> RCLK<27..0> RCLK<27..0>
E
PCI1_AD<31..0> PCI1_C/BEB<3..0> PCI1_PAR PCI1_FRAMEB PCI1_TRDYB PCI1_IRDYB PCI1_STOPB PCI1_DEVSELB PCI1_LOCKB PCI1_PERRB PCI1_SERRB FREEDM_SCLK FREEDM_INTB PCI1_RSTB PCI1_REQB_FREEDM PCI1_GNTB_FREEDM TDO_FREEDM TRSTB_PCI TMS_PCI TCK_PCI TDO_PCI
PCI1_AD<31..0> PCI1_C/BEB<3..0> PCI1_PAR PCI1_FRAMEB PCI1_TRDYB PCI1_IRDYB PCI1_STOPB PCI1_DEVSELB PCI1_LOCKB PCI1_PERRB PCI1_SERRB
F
E PCI_PCI_BRIDGE PCI1_AD<31..0> PCI1_C/BEB<3..0> PCI1_PAR PCI1_FRAMEB PCI1_TRDYB PCI1_IRDYB PCI1_STOPB PCI1_DEVSELB PCI1_LOCKB PCI1_PERRB PCI1_SERRB PCI1_RSTB PCI1_REQB_FREEDM PCI1_GNTB_FREEDM D
TDO_FREEDM LOCAL_PCI_BRIDGE D
PAGE 5
PCI1_RSTB PCI1_REQB_FREEDM PCI1_GNTB_FREEDM
RSTB_TEMUX INTB_TEMUX CSB_TEMUX WRB_TEMUX RDB_TEMUX D_TEMUX<7..0> A_TEMUX<13..0>
PCI1_AD<31..0> PCI1_C/BEB<3..0> PCI1_PAR PCI1_FRAMEB PCI1_TRDYB PCI1_IRDYB PCI1_STOPB PCI1_DEVSELB PCI1_LOCKB PCI1_PERRB PCI1_SERRB PCI1_RSTB FREEDM_SCLK FREEDM_INTB PCI9054_SCLK PCI9054_INTB PCI9054_SCLK PCI9054_INTB FREEDM_SCLK FREEDM_INTB PCI_5V PCI9054_SCLK PCI9054_INTB RESETB TDO_PCI TRSTB_PCI TMS_PCI TCK_PCI TDO_CPLD C
LCLK C
POWER_BLOCK
PAGE 7 TDO_TEMUX TDO_PCI TRSTB_PCI TMS_PCI TCK_PCI TDO_CPLD PAGE 8,9
TDO_CPLD TRSTB_PCI TMS_PCI TCK_PCI TDO_TEMUX
B RESETB PCI_5V RESETB PCI_5V
B
PAGE 10
ROOT DRAWING
PMC-Sierra, Inc.
A DRAWING TITLE=FREEDM_32P672_DS3_LIU_ROOT ABBREV=FREEDM32P672_DS3 LAST_MODIFIED=Tue Feb 8 11:00:09 2000 10 9 8 7 6 5 4 3
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 08, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN ROOT_DRAWING ENGINEER: TN 2 REVISION NUMBER: 0 PAGE:1 1 OF 9
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T3 LINE INTERFACE
H
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DESCRIPTION
DATE
APPR
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G
G
3.3 V
R11
J2
T TN RN R S
T TN RN R S 1
T1
1:1 1
33 6
1
6
R9 7 17 26
DECOUPLING
75
2B10<
F
RX BANTAM
3F10> 3F10> 3F10>
F
U1 LIN+ LINTCLK TPOS TNEG RCLK RPOS TXEN RNEG MON ICKP 78P2241 LOUT+ E3 LOUTLPBK ENDEC LOS RFO LF1 VCC VCC VCC GND GND GND GND GND LBO
2 4 6 8 22 12
44
CHASSIS GROUND FOR ISOLATION TCLK_TEMUX\I TPOS_TEMUX\I TNEG_TEMUX\I 3.3 V
PE-65966
TOLERANCE 3% 75 OHM 75 OHM 75 OHM
10K R8
1 3 16 14 15 18 21 10 13 28 20 5 19
23 25 24 9 11 27
75 OHM 75 OHM 75 OHM 3.3 V
1
RCLK_LIU\I RPOS_LIU\I RNEG_LIU\I T2
2:1 1 6 44
6 2 T TN RN R S
4E10< 4E10< 4E10<
10K R5
J5
T TN RN R S
E
DEFAULT IS NON INVERTED ICKP IS DEFAULT LOW (3&4 SHORTED)
10K
R14
3.3 V
R2
10K R6 100K R7 5.23K R10 0.047UF
301
2 33
0.1UF
TX BANTAM E
J1 P_1 P_2 P_3 P_4 ICKP
1 2 3 4
PE-65969
TOLERANCE 3%
C8
CHASSIS GROUND FOR ISOLATION
3.3 V
10K R3
J3 P_1 P_2 P_3 P_4 LPBK
1 2 3 4 10K R1
3.3 V
10K R12
1
TP1 297P HDR1 PROBE POINT TO MONITOR LIN+ AND LIN-, ACTIVE LOW INDICATES SIGNAL LOSS
C7
J4
1 2 3 4
DEFAULT IS NO LOOP BACK LPBK IS DEFAULT HIGH (2&3 SHORTED) D
P_1 P_2 P_3 P_4 LBO LPBK IS DEFAULT HIGH (2&3 SHORTED) LOW FOR CABLE LENGTH >= 225FT HIGH FOR CABLE LENGTH < 225FT
10K
R4
10K
R13
D
C
C
PLACE DECOUPLING CAPS NEAR POWER PINS DECOUPLING B
4.7UF 4.7UF 4.7UF 0.01UF 0.01UF 0.01UF C1 C2 C3
2F5>
B
C4
C5
C6
T3 LINE INTERFACE
PMC-Sierra, Inc.
A DRAWING TITLE=T3_LINE_INTERFACE ABBREV=T3_LINE_INTERFACE LAST_MODIFIED=Wed Feb 9 18:14:52 2000 DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 08, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN T3_LINE_INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 TN 2 REVISION NUMBER: 0 PAGE:2 1 OF 9 A
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TEMUX EGRESS (1/2)
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DESCRIPTION
DATE
APPR
H
3.3 V
AA12
2.5 V
AA15
L21
C12
AA8
R21
H21
A15
N2
J2
R2
PBGA U2
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDD2V5<8>
VDD2V5<7>
VDD2V5<6>
VDD2V5<5>
VDD2V5<4>
VDD2V5<3>
VDD2V5<2>
VDD2V5<1>
C9
G
G
P1 N1 P4 M3 N4 M2 C5 A4 L2 L1 B5 A5 E22 C20 B6 D4 M1 P2 C7 D6 M22 N19 B4 A3 R4 T2 A2 A7 N22 N21 N20 P19 AA3 AB4 F2 E4 K4 L3 D20 B22 U22 T20 F1 D3 R1 U4 C21 D21 V19 U21 G3 G2 T1 AB1 T22 T21 V22 AB22 AA21 Y19 Y4 AB3 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1>
330 R25
3.3 V RN11 4.7K
8 7 6 5
330 R26
W12 AB10 AA10 Y10 W9 AB9 W8 W7 AB8 W13 AA11 W10 Y11 AB11 AB7 W6 AA6 AA7 A16 D16 B16 C15 D17
LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB CSB RDB WRB ALE D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB
FOR T1 USE 12.352 MHZ (DEFAULT) FOR E1 USE 16.384 MHZ CTCLK\I TD<27..0>\I
6D4> 5E10>
1 2 3 4
RES_ARRAY_4
F
2F10< 2F10< 6E4> 2F10< 7F1< 7F1> 7F1> 7F1> 7G4<>
TPOS_TEMUX\I TNEG_TEMUX\I TICLK\I TCLK_TEMUX\I INTB_TEMUX\I CSB_TEMUX\I RDB_TEMUX\I WRB_TEMUX\I
F
75 OHM 75 OHM 75 OHM
51 51 51
R96 R97 R98
4.7K
R59 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D_TEMUX<7..0>\I
E
7C4>
D13 A13 B13 C13 D14 A14 B14 C14 B21 C19 A21 B20 B19 C18 A20 A19 A18 B17 D19 D18 C16 A17 A22
TEMUX PM8315 1 OF 2
TCLK<27..0>\I
5E7<
A_TEMUX<13..0>\I
E
7E1>
RSTB_TEMUX\I
D
D
L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9
N3 Y12 L20 B12
EGRESS DIRECTION, TEMUX IN CLOCK MASTER: NXCHANNEL MODE C C
3.3 V
DECOUPLING CAPACITORS FOR VDD 3.3V
0.01UF
C41 0.01UF
C43 0.01UF
C45 0.01UF
C47
J3 R3 Y8 Y15 R20 H20 B15 B9
VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1>
VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1>
B
B
2.5 V
DECOUPLING CAPACITORS FOR VDD 2.5V
TEMUX EGRESS (1/2)
PMC-Sierra, Inc.
0.01UF
C42 0.01UF
C44 0.01UF
C46 0.01UF
C48 0.01UF
C50 0.01UF
C52 0.01UF
C54 0.01UF
C56
A DRAWING TITLE=TEMUX_BLOCK ABBREV=TEMUX LAST_MODIFIED=Wed Feb
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 08, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN TEMUX EGRESS (1/2) 9 18:15:01 2000 ENGINEER: TN 2 PAGE:3 1 OF 9 REVISION NUMBER: 0
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
TEMUX INGRESS (2/2)
H
ZONE
REV
DESCRIPTION
DATE
APPR
H
3.3 V G
AA14 AA9 Y18 U20 M21 F20 C17
G
PBGA U2
B11 F3 M4 U3 Y5 D5
VDD3V3<9>
VDD3V3<8>
VDD3V3<7>
VDD3V3<6>
VDD3V3<5>
VDD3V3<4>
VDD3V3<3>
VDD3V3<2>
VDD3V3<13>
VDD3V3<12>
VDD3V3<11>
330 R56
146P 330 RN12
P3 W17 AB15 W16 W15 AB14 W14 Y13 AA13 Y16 AB16 AA16 AB17 AB12 AB13 AA17 AB18 W18 AA18 AB19 W19 R57 R58 R60 R61 W5 Y7 AB6 E20 C3 C2 C4 B3 B1
VDD3V3<10>
VDD3V3<1>
CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TCK TMS TDI TDO TRSTB
CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1>
T4 B7 A6 D7 A8 C8 C10 B10 H4 J1 A10 D10 L19 M19 A11 D11 V4 U2 D12 A12 P22 P21 H2 G4 W2 Y2 G21 G22 P20 R19 T19 AA20 Y6 AA5 D2 E3 J4 K3 F21 E19 G19 H19 C1 D1 U1 T3 G20 F22 K19 L22 H1 H3 AA1 W3 F19 H22 Y20 W22 AB21 AB20 AB2 Y3 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 330 330 330 R62 R63 R64 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R102 R103 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
1 8 2 7 3 6 145P 4 330 RN21 5 1 8 RES_4_ARRAY 2 7 3 6 147P 4 330 RN13 5 1 8 RES_4_ARRAY 2 7 3 6 144P 4 330 RN7 5 1 8 RES_4_ARRAY 2 7 3 6 4 5 148P
RES_4_ARRAY
RD<27..0>\I
5H10<
F
330 RN14
8 7 6 5
RES_4_ARRAY
1 2 3 4 51 51 51 51
2F2> 2F2> 2E2> 6F4>
RCLK_LIU\I RPOS_LIU\I RNEG_LIU\I XCLK\I TCK_PCI\I TMS_PCI\I TDO_FREEDM\I TDO_TEMUX\I TRSTB_PCI\I
75 OHM 75 OHM 75 OHM
E
8H6> 8G6> 5F1> 7E1< 8H6>
E
TEMUX PM8315 2 OF 2
RCLK<27..0>\I
5H7<
D
A9 D8 K2 K1 J20 J22 R22 U19 D9 E1 V1 W4 J19 K20 Y22 V20 G1 F4 W1 Y1 K21 K22 W21 Y21 AA22 W20 V3 AB5 C22 D22
IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1
TEMUXSELB
D
C
VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1>
VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21>
C
AA2 J14 J13 J12 J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11
INGRESS DIRECTION, TEMUX IN CLOCK MASTER: FULL T1/E1 MODE
E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21 M20 J21 E21 B18 D15 C11 B8 C6
B
B
3.3 V
DECOUPLING CAPACITORS FOR VDDO AND VDD3V3
TEMUX INGRESS (2/2)
0.01UF C49 0.01UF C51 0.01UF C53 0.01UF C55 0.01UF C57 0.01UF C58 0.01UF C59 0.01UF C60 0.01UF C61 0.01UF C62 0.01UF C63 0.01UF C64 0.01UF C65
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 08, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN TEMUX INGRESS (2/2) 9 18:15:04 2000 ENGINEER: TN 2 PAGE:4 1 OF 9 REVISION NUMBER: 0 A
A DRAWING TITLE=TEMUX_BLOCK ABBREV=TEMUX LAST_MODIFIED=Wed Feb
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
RN3
1 2 3 4
RES_4_ARRAY
330
8 7 6 5
RN5
1 2 3 4
330
8 7 6 5
FREEDM32P672
ZONE
REV
DESCRIPTION
DATE
APPR
H
H RCLK<27..0>\I
U3
C12 B13 D13 B14 C15 D15 C16 A16 A17 A18 A19 B20 D19 B21 D20 A22 C23 E20 D22 E23 F23 G23 G22 H23 J20 J21 K21 L23 L22 M21 N22 N20 C17 A23 H22 P21 P23 R22
RES_4_ARRAY
4F2>
RD<27..0>\I
G
RN1
8 7 6 5
330
1 2 3 4
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
RES_4_ARRAY
3
6
RES_ARRAY_4
RN8
5
330
4
4.7K
RECEIVE BIT ERROR RATE TEST DATA AND CLOCK
8 7 6 5
RN4
330
1 2 3 4
U3
AB4 AC5 AC6 AC7 AB7 AC8 AA8 Y9 AB10 Y11 AB11 AA12 AB13 AC13 AA14 AC14 AC15 AB16 AA17 Y17 AB18 AA18 AA19 AC20 AC21 AC22 AB23 Y20 AA22 W20 Y22 W23 AB9 AA15 Y19 V21 V22 U20
1 2 3 4
RN6
330
8 7 6 5 P14 P13 P12 P11 P10 N14 N13 N12 N11 N10 M14 M13 M12 M11 M10 L14 L13 L12 L11 L10 K14 K13 K12 K11 K10 Y16 Y12 Y8 V20 V4 P20 P4 K20 K4 F20 F4 D16 D12 D8
U3 FREEDM-32P672 VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VDD3V3<14> VSS<32> VDD3V3<13> VSS<31> VDD3V3<12> VSS<30> VDD3V3<11> VSS<29> VDD3V3<10> VDD3V3<9> VSS<28> VDD3V3<8> VSS<27> VDD3V3<7> VSS<26> VDD3V3<6> VSS<25> VDD3V3<5> VSS<24> VDD3V3<4> VSS<23> VDD3V3<3> VSS<22> VDD3V3<2> VSS<21> VDD3V3<1> VSS<20> VSS<19> VSS<18> VDD2V5<12> VSS<17> VDD2V5<11> VSS<16> VDD2V5<10> VSS<15> VDD2V5<9> VSS<14> VDD2V5<8> VSS<13> VDD2V5<7> VSS<12> VDD2V5<6> VSS<11> VDD2V5<5> VSS<10> VDD2V5<4> VDD2V5<3> VSS<9> VDD2V5<2> VSS<8> VDD2V5<1> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> POWER 4 OF 4 PM7380
E
3F2<
RES_4_ARRAY
RES_4_ARRAY
TD<27..0>\I
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4
RES_4_ARRAY
D
RN2
8 7 6 5 8
330
7
2
RES_ARRAY_4
RN8
1
330
C
RN8
RES_ARRAY_4
330
FREEDM-32P672 TCLK<31> TD<31> TCLK<30> TD<30> TCLK<29> TD<29> TCLK<28> TD<28> TCLK<27> TD<27> TCLK<26> TD<26> TCLK<25> TD<25> TCLK<24> TD<24> TCLK<23> TD<23> TCLK<22> TD<22> TCLK<21> TD<21> TCLK<20> TD<20> TCLK<19> TD<19> TCLK<18> TD<18> TCLK<17> TD<17> TCLK<16> TD<16> TCLK<15> TD<15> TCLK<14> TD<14> TCLK<13> TD<13> TCLK<12> TD<12> TCLK<11> TD<11> TCLK<10> TD<10> TD<9> TCLK<9> TD<8> TCLK<8> TD<7> TCLK<7> TD<6> TCLK<6> TD<5> TCLK<5> TD<4> TCLK<4> TD<3> TCLK<3> TD<2> TCLK<2> TD<1> TCLK<1> TD<0> TCLK<0> TFPB<3> TMVCK<3> TFPB<2> TMVCK<2> TFPB<1> TMVCK<1> TFPB<0> TMVCK<0> TMV8FPC TFP8B TMV8DC TBD 2 OF 4 TBCLK PM7380 TRANSMIT
4.7K
RN8
RES_ARRAY_4
330
FREEDM-32P672 RD<31> RCLK<31> RD<30> RCLK<30> RD<29> RCLK<29> RD<28> RCLK<28> RD<27> RCLK<27> RD<26> RCLK<26> RD<25> RCLK<25> RD<24> RCLK<24> RD<23> RCLK<23> RD<22> RCLK<22> RD<21> RCLK<21> RD<20> RCLK<20> RD<19> RCLK<19> RD<18> RCLK<18> RD<17> RCLK<17> RD<16> RCLK<16> RD<15> RCLK<15> RD<14> RCLK<14> RD<13> RCLK<13> RD<12> RCLK<12> RD<11> RCLK<11> RD<10> RCLK<10> RD<9> RCLK<9> RD<8> RCLK<8> RD<7> RCLK<7> RD<6> RCLK<6> RD<5> RCLK<5> RD<4> RCLK<4> RD<3> RCLK<3> RD<2> RCLK<2> RD<1> RCLK<1> RD<0> RCLK<0> RMVCK<3> RFPB<3> RMVCK<2> RFPB<2> RMVCK<1> RFPB<1> RMVCK<0> RFPB<0> RMV8FPC RFP8B RMV8DC RBD RECEIVE RBCLK 1 OF 4 PM7380
B12 C13 A13 C14 A14 B15 A15 B16 D17 B18 C18 C19 A20 C20 A21 B22 C21 D21 D23 E21 F21 F22 G20 G21 J23 J22 K22 L20 L21 M22 N21 N23 B17 B23 H21 P22 R21 R23 R20
4E2> 8H10<> 7G10<>
U3
PCI1_AD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H3 J1 J4 J2 J3 K1 K2 K3 L2 L3 M3 M2 N2 N3 N1 N4 U2 U4 U1 V2 V1 V3 W1 W3 Y1 W4 Y3 AA2 AA1 AA3 AB1 AC1
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4
5G1<
PCI1_IDSEL_FREEDM 20 DEVICE #4
RN9
330
8 7 6 5
TP2 HDR1 1 RBD HDR1 1 TP3 RECLK
RES_4_ARRAY
FREEDM-32P672 AD<31> AD<30> C/BEB<3> AD<29> C/BEB<2> AD<28> C/BEB<1> AD<27> C/BEB<0> AD<26> PAR AD<25> FRAMEB AD<24> TRDYB AD<23> IRDYB AD<22> STOPB AD<21> DEVSELB AD<20> IDSEL AD<19> LOCKB AD<18> REQB AD<17> GNTB AD<16> PERRB AD<15> SERRB AD<14> PCIINTB AD<13> PCICLK AD<12> PCICLKO AD<11> AD<10> M66EN RSTB AD<9> SYSCLK AD<8> PMCTEST AD<7> AD<6> TDO AD<5> TDI AD<4> TCK AD<3> TMS AD<2> TRSTB AD<1> PCI AD<0> 3 OF 4 PM7380
PCI1_C/BEB<3..0>\I
L4 P3 U3 Y2 T1 P2 R3 P1 R4 R2 L1 R1 H2 H1 T3 T2 G1 G3 G4 AC2 C22 K23 AB3 U22 U21 T23 T22 T21 R24 R23 3 2 1 0
7E10<> 8F10<>
PCI1_PAR\I PCI1_FRAMEB\I PCI1_TRDYB\I PCI1_IRDYB\I PCI1_STOPB\I PCI1_DEVSELB\I PCI1_IDSEL_FREEDM PCI1_LOCKB\I PCI1_REQB_FREEDM\I PCI1_GNTB_FREEDM\I PCI1_PERRB\I PCI1_SERRB\I FREEDM_INTB\I FREEDM_SCLK\I
51 R95
7E10<> 8E10<> 7E10<> 8E10<> 7D10<> 8E10<> 7D10<> 8E10<> 7E10<> 8E10<> 7E10<> 8E10<> 5G6> 8E10> 8E10< 8F10> 7E10<> 8E10<> 7E10> 8E10< 8G6< 8D9> 8D9>
G
PCI1_RSTB\I TDO_FREEDM\I TDO_PCI\I TCK_PCI\I TMS_PCI\I TRSTB_PCI\I
4E10< 8G6> 8H6> 8G6> 8H6>
F 3.3 V
R168
330
SET M66EN LOW FOR 33MHZ PCI BUS
AC4 AA5 AA6 AB6 Y7 AA7 AB8 AC9 AC10 AA10 AC11 AA11 AB12 AA13 Y13 AB14 Y15 AA16 AC16 AB17 AC17 AC18 AC19 AB20 AB21 AA21 AC23 AB22 AA23 Y21 Y23 W21 AA9 AB15 AA20 V23 U23 Y5 AA4 1 1
E 3.3 V
Y18 Y14 Y10 Y6 T20 T4 M20 M4 H20 H4 D18 D14 D10 D6 B5 A12 B19 E22 W22 AB19 AC12 AB5 W2 M1 E2 M23
TCLK<27..0>\I
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3E2>
2.5 V D
RN10
1 2 3 4
330
8 7 6 5
TP4 TP5 HDR1 TBD HDR1 TBCLK
RES_4_ARRAY
R169
330
C
TRANSMIT BIT ERROR RATE TEST DATA AND CLOCK
3.3 V
DECOUPLING CAPACITORS FOR VDD 3.3V
0.01UF
C15 0.01UF
C17 0.01UF
C19 0.01UF
C21 0.01UF
C23 0.01UF
C25 0.01UF
C27 0.01UF
C29 0.01UF
C32 0.01UF
C34 0.01UF
C36 0.01UF
C38 0.01UF
C39 0.01UF
C40
B
B
FREEDM32P672
2.5 V DECOUPLING CAPACITORS FOR VDD 2.5V
PMC-Sierra, Inc.
0.01UF C16 0.01UF C18 0.01UF C20 0.01UF C22 0.01UF C24 0.01UF C26 0.01UF C28 0.01UF C30 0.01UF C31 0.01UF C33 0.01UF C35 0.01UF C37
A
DRAWING TITLE=FREEDM_32P672_BLOCK ABBREV=FREEDM32P672 LAST_MODIFIED=Wed Feb 9 18:14:58 2000
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 15, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN FREEDM32P672 ENGINEER: TN 2 REVISION NUMBER: 0 PAGE:5 1 OF 9
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
OSCILLATOR BLOCK
H
ZONE
REV
DESCRIPTION
DATE
APPR
H
G
G
3.3 V SOCKETED
0.01UF C9 0.1UF
Y1
C12
TEMUX
OSC_EP26
4 2
VCC GND
OUTPUT TS/PD
3 1
51 R15
XCLK\I
4E10<
37.056MHZ F F
3.3 V SOCKETED
0.01UF C10 0.1UF
Y2
C13
OSC_EP26
4 2
TEMUX
VCC GND
OUTPUT TS/PD
3 1
51 R16
TICLK\I
3F10<
44.736MHZ E E
3.3 V SOCKETED
0.01UF C11 0.1UF
Y3
C14
TEMUX
3V3
4
8 5 51 R17
GND
OUT
CTCLK\I
3G2<
D
12.352MHZ 25PPM FOR T1 USE 12.352 MHZ (DEFAULT) FOR E1 USE 16.384 MHZ
D
3.3 V SOCKETED
0.01UF
PCI9054 & CPLD
C73
C
C72 0.1UF
Y4 C 3V3
4 8 5 51 R99
GND 8.000MHZ 25PPM
OUT
LCLK\I
7E5<
B
B
OSCILLATOR BLOCK
PMC-Sierra, Inc.
A DRAWING TITLE=OSCILLATORS ABBREV=OSCILLATOR_BLOCK LAST_MODIFIED=Wed Feb 9 18:14:54 2000 DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 15, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN OSCILLATORS ENGINEER: 10 9 8 7 6 5 4 3 TN 2 REVISION NUMBER: 0 PAGE:6 1 OF 9 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
LOCAL TO PCI BRIDGE & CPLD
H
ZONE
REV
DESCRIPTION
DATE
APPR
H
LD<31..8>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D_TEMUX<7..0>\I
3E10<>
U10
95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
8H10<> 5H6<>
LD<31> LD<30> LD<29> LD<28> LD<27> LD<26> LD<25> LD<24> LD<23> LD<22> LD<21> LD<20> LD<19> LD<18> LD<17> LD<16> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> LD<2> LD<1> LD<0>
G
PCI1_AD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 6 16 30 41 167 52 29 22 23 26 25 24 17 21 18 7 172 169 4.7K R108 171 170 168
3.3 V
VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0>
162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 139 138 137 136 134 163 144 143 148 90 149 135 146 145 91 92 153 151 150 160 142 53 154 152 159 158 157 156 155 176 161 140 132 115 108 88 69 61 44 27 19
3.3 V SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE GND VCC3V3
G RN20
8 7 6 5
7D10<
24
HDR14
PCI1_IDSEL_9054 DEVICE #8
F
8F10<> 5H1<>
4.7K RN15
8 7 6 5
E
8E10<> 5G1<> 8E10<> 5G1<> 8E10<> 5G1<> 8E10< 5G1> 8E10<> 5G1<> 8E10> 8E10<> 5G1<> 8E10<> 5G1<> 8E10<> 5G1<> 7G10> 8D9> 8D9> 8G6<
1 2 3 4
IO214 IO215 IO216 IO217 IO117 GND2 IO116 VCINT1 IO115 IO114 IO113
PCI1_C/BEB<3..0>\I 3.3 V
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
4.7K RN16
4.7K RN18
8 7 6 5
8 7 6 5
4.7K RN19
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
8 7 6 5
RES_4_ARRAY
4.7K
J13 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10 P_11 P_12 P_13 P_14
3.3 V
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
3.3 V
40 41 42 43 44 1 2 3 4 5 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3.3 V GTS2_IO205 VCCINT2 GTS1_IO203 IO204 IO202 IO201 IO101 IO102 IO104 GCK1_IO103 GCK2_IO105
U12 F GCK3_IO107 IO106 IO108 GND1 IO109 IO110 IO111 IO112 TDI TMS TCK
7 8 9 10 11 12 13 14 15 16 17
BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS* LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
39 38 HOLD_9054 37 W_RB_9054 READYB_9054 36 ADSB_9054 35 34 33 32 31 30 29
PCI9054 C-MODE
C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA*
GSR_IO206 IO207 IO208 IO209 IO210 IO211 IO212 VCIO GND3 TDO IO213
INTB_TEMUX\I RDB_TEMUX\I WRB_TEMUX\I CSB_TEMUX\I RSTB_TEMUX\I TDO_TEMUX\I TMS_PCI\I TCK_PCI\I TDO_CPLD\I
3F10> 3F10< 3F10< 3F10< 3D10< 4E10> 8G6> 8H6> 8G6<
XC9536XL_PC44
J14
1 3 5 7 2 4 6 8
CPLD H4
PROGRAMMING CPLD OR JTAG TEST 3.3 V
E
PCI1_PAR\I PCI1_DEVSELB\I PCI1_STOPB\I PCI1_SERRB\I PCI1_PERRB\I PCI1_LOCKB\I PCI1_FRAMEB\I PCI1_TRDYB\I PCI1_IRDYB\I PCI1_IDSEL_9054 PCI1_RSTB\I PCI9054_SCLK\I PCI9054_INTB\I
INTB_9054 RESETB_9054
2 1
J11
6C4>
LCLK\I 3.3 V
330 RN17
1 2 3 4
RES_4_ARRAY
1 2 3 4 5 6 7 8 9 10
28 27 26 25 24 23 22 21 20 19 18
RES_4_ARRAY
EEDI/O EESK EECS
D
LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> LA<29> LA<30> LA<31>
J12 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10
HDR10
D
8 7 6 5
3.3 V
4.7K 4.7K
DIP8_SOCKET U9
NM93CS56
8 R109 7 6 R110 5
VCC PRE PE GND
CS SK DI DO
1 2 3 4
166 165 164
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
94 93 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54
LA<31..14>
A_TEMUX<13..0>\I C
3E10<
GND VCC3V3 SPARE SPARE SPARE SPARE SPARE SPARE SPARE
C
3.3 V
3.3 V
4.7K RN27 8
4.7K RN28 8
4.7K RN29 8
4.7K RN30 8
4.7K RN31 8
4.7K RN32 8
4.7K RN33 8
4.7K RN34 8
4.7K RN35 8
4.7K RN36 8
4.7K RN37 8
7 6 5
7 6 5
7 6 5
7 6 5
7 6 5
7 6 5
7 6 5
7 6 5
7 6 5
RES_4_ARRAY
RES_4_ARRAY
7 6 5
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
RES_4_ARRAY
7 6 5
RES_4_ARRAY
B
3.3 V
DECOUPLING CAPACITORS FOR VDD 3.3V
B
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
0.01UF
C74 0.01UF
C75 0.01UF
C77 0.01UF
C79 0.01UF
C81 0.01UF
C89 0.01UF
C91 0.01UF
C95 0.01UF
C99 0.01UF
1 2 3 4
1 2 3 4
C101
LOCAL TO PCI BRIDGE & CPLD
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
LA<31..14>
30 31
28 29 30 31
LD<31..8>
C96 0.01UF
C100 0.01UF
0.01UF
C76 0.01UF
C78 0.01UF
C80 0.01UF
C82 0.01UF
C90 0.01UF
C94 0.01UF
PMC-Sierra, Inc.
C104
A DRAWING TITLE=LOCAL_PCI_BRIDGE ABBREV=LOCAL_PCI_BRIDGE LAST_MODIFIED=Wed Feb 9 18:15:11 2000
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* DEC. 9, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN LOCAL_PCI_BRIDGE & CPLD ENGINEER: TN 2 REVISION NUMBER: 0 PAGE:7 1 OF 9
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
S_VIO = P_VIO = 3.3V PRIMARY AND SECONDARY BUSES ARE BOTH 3.3V SIGNALING ENVIRONMENT
52 67
3.3 V
8 15 23 30 40 46 56 60 75 80 90 98 108 116 120 125 131 139 147 154 160
PCI TO PCI BRIDGE
PCI_AD<31..0> P_AD<31> P_AD<30> P_AD<29> P_AD<28> P_AD<27> P_AD<26> P_AD<25> P_AD<24> P_AD<23> P_AD<22> P_AD<21> P_AD<20> P_AD<19> P_AD<18> P_AD<17> P_AD<16> P_AD<15> P_AD<14> P_AD<13> P_AD<12> P_AD<11> P_AD<10> P_AD<9> P_AD<8> P_AD<7> P_AD<6> P_AD<5> P_AD<4> P_AD<3> P_AD<2> P_AD<1> P_AD<0> P_CBE_I<3> P_CBE_I<2> P_CBE_I<1> P_CBE_I<0> P_DEVSEL_I P_FRAME_I P_GNT_I P_IDSEL P_IRDY_I P_LOCK_I P_PAR P_PERR_I P_REQ_I P_SERR_I P_STOP_I P_TRDY_I
70 72 73 74 76 77 78 79 84 85 87 88 89 91 92 93 109 110 111 113 114 115 117 118 123 124 126 127 129 130 132 133 82 95 107 122 100 96 68 83 97 102 106 104 69 105 101 99 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
ZONE
REV
DESCRIPTION
DATE
APPR
H U11
7G10<> 5H6<>
H
PCI1_AD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 36 35 33 32 31 29 28 26 24 22 21 20 18 17 16 14 156 155 153 152 150 149 148 146 144 142 141 140 138 137 136 134 25 13 158 145 47 45 44 43 42 39 38 37 49 7 11 10 5 2 4 3 6 9
G CARD TO HOST
7E10<> 5H1<>
PCI1_C/BEB<3..0>\I 3.3 V 4.7K RN22
8 7 6 5
RES_4_ARRAY
S_AD<31> S_AD<30> S_AD<29> S_AD<28> S_AD<27> S_AD<26> S_AD<25> S_AD<24> S_AD<23> S_AD<22> S_AD<21> S_AD<20> S_AD<19> S_AD<18> S_AD<17> S_AD<16> S_AD<15> S_AD<14> S_AD<13> S_AD<12> S_AD<11> S_AD<10> S_AD<9> S_AD<8> S_AD<7> S_AD<6> S_AD<5> S_AD<4> S_AD<3> S_AD<2> S_AD<1> S_AD<0>
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21
S_VIO P_VIO
P1
7E1< 7E1< 5F1< 4E10< 5F1< 4E10< 5F1< 4E10< 5F1< 7E1>
TRSTB_PCI\I TCK_PCI\I TMS_PCI\I TDO_PCI\I TDO_CPLD\I
A1 A2 A3 A4 A5
TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +VI/O RESERVED
-12V TCK GROUND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2#
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
NOTE:
USE 5V BACKPLANE SIGNALING ENVIRONMENT NOTE THE V_I/O PINS ARE NOT USED
7D10> 5G1>
PCI9054_INTB\I FREEDM_INTB\I
A6 A7 A8 A9 A10 A11
G
21152
A14
PCI_C/BEB<3..0>
A15 A16 A17 A18 A19 A20 A21 A22 A23 A24
3.3VAUX RST# +VI/O GNT# GROUND PME# AD[30] +3.3V AD[28] AD[26] GROUND AD[24] IDSEL +3.3V AD[22] AD[20] GROUND AD[18] AD[16] +3.3V FRAME# GROUND TRDY# GROUND STOP# +3.3V RESERVED RESERVED GROUND PAR AD[15] +3.3V AD[13] AD[11] GROUND AD[09]
RESERVED GROUND CLK GROUND REQ# +VI/O AD[31] AD[29] GROUND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GROUND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GROUND IRDY# +3.3V DEVSEL# GROUND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GROUND AD[12] AD[10] GROUND
B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 24 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 18 17 16 2 22 21 20 19 23 3 28 27 26 25 31 30 29
F
1 2 3 4
S_CBE_I<3> S_CBE_I<2> S_CBE_I<1> S_CBE_I<0> S_GNT_I<3> S_GNT_I<2> S_GNT_I<1> S_GNT_I<0> S_REQ_I<3> S_REQ_I<2> S_REQ_I<1> S_REQ_I<0> S_CFN_I S_DEVSEL_I S_FRAME_I S_IRDY_I S_LOCK_I S_PAR S_PERR_I S_SERR_I S_STOP_I S_TRDY_I
F
5G1<
PCI1_GNTB_FREEDM\I
4.7K 4.7K R104 R105
5G1> 7E10<> 5G1<> 7E10<> 5G1<> 7D10<> 5G1<> 7E10<> 5G1<>
PCI1_REQB_FREEDM\I PCI1_DEVSELB\I PCI1_FRAMEB\I PCI1_IRDYB\I PCI1_LOCKB\I PCI1_PAR\I PCI1_PERRB\I PCI1_SERRB\I PCI1_STOPB\I PCI1_TRDYB\I
4.7K
1 2 3 4
RN25
8 7 6 5
A25
RES_4_ARRAY
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 S_CLK_O<4> S_CLK_O<3> S_CLK_O<2> S_CLK_O<1> S_CLK_O<0>
RES_4_ARRAY
E
A26 A27 A28 A29 A30
S_CLK S_RST_I P_RST_I P_CLK NAND_OUT GOZ_I BPCC
RN26
4.7K
7E10> 5G1> 7E10<> 5G1<> 7D10<> 5G1<>
E
8 7 6 5
R100
3.3 V
8 7 6 5
4.7K RN23
4.7K RN24
RES_4_ARRAY
8 7 6 5
RES_4_ARRAY
1 12 19 27 34 41 50 54 58 65 71 81 86 94 103 112 119 121 128 135 143 151 157
61 59 57 55 53
51 48 64 66 62 63 159
1 2 3 4
1K0
A31 A32 A33
1 2 3 4
1 2 3 4
7D10<
PCI9054_SCLK\I FREEDM_SCLK\I PCI1_RSTB\I
51 R106 51 R107
51 R164
3.3 V
A34
U7
4 6
A35 A36
D
5G1< 7D10< 5G1<
74HC08
5
RESETB\I
9B6>
D
A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 13 12 11 10 9 15 14 1
PCI_5V\I
9G10<
C
A47 A48 A49 0
C
A52 A53 A54 A55
C/BE[0]# +3.3V AD[06] AD[04] GROUND AD[02] AD[00] +VI/O REQ64# +5V +5V
AD[08] AD[07] +3.3V AD[05] AD[03] GROUND AD[01] +VI/O ACK64# +5V +5V
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
8 7 6 5 4 3
3.3 V B
DECOUPLING CAPACITORS FOR VDD 3.3V
A56 A57 A58 C97 0.01UF C102 0.01UF C107 0.01UF C111 0.01UF C115 0.01UF C119 0.01UF
B
2 1 0
0.01UF
C83 0.01UF
C86 0.01UF
C92 0.01UF
C123 0.01UF
C84 0.01UF
A59 C85 A60 A61 A62
PCI TO PCI BRIDGE
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 17, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN PCI_PCI_BRIDGE REVISION NUMBER: 0 PAGE:8 2 1 OF 9 A
C98 0.01UF
C103 0.01UF
C108 0.01UF
C112 0.01UF
C116 0.01UF
C120 0.01UF
C124 0.01UF
0.01UF
C87 0.01UF
C93 0.01UF
C127 0.01UF
PCI_UNIV_32BIT_CARD_CONNECTOR
C88
A DRAWING TITLE=PCI_PCI_BRIDGE ABBREV=PCI_PCI_BRIDGE LAST_MODIFIED=Wed Feb
9 18:15:16 2000 ENGINEER: TN
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
POWER BLOCK
H
ZONE
REV
DESCRIPTION
DATE
APPR
H
G
5V SUPPLY FROM PCI CONNECTOR U8
8D1>
2.5 V 2.5V
1 0.1UF 22UF 220 R93
G
PCI_5V\I
2.2UF
F1
470 R91
3 10UF
3.000A
C67
LT1118CST VIN VOUT TAB GND GND
2 4
C109
C69
C70
BULK DECOUPLING CAPACITOR FOR VDD 2.5V
22UF
C71
2
D1
1
2
+5.0V DC SUPER_GREEN
D3
1
+2.5V DC SUPER_GREEN
2
F D4
SCHOTTKY DIODE TO ENSURE THAT 3.3V IS POWERED UP BEFORE AND POWERED DOWN AFTER THE 2.5V SUPPLY TO SATISFY TEMUX AND FREEDM32P672 REQUIRMENTS
F
1
3.3 V E
33 10UF
LT1117CST
U5 3.3V
VOUT
VIN
22 C66 0.22UF 22UF
E
22UF
ADJ/GND
C68
BULK DECOUPLING CAPACITORS FOR VDD 3.3V
C105
C106
2
330
R92
11
D2
1
+3.3V DC SUPER_GREEN
D
D
C
C
3.3 V U6 SW1
2
PBNO
VCC
MAX811S
1 3
4
MR
RESET GND
1
2
RESETB\I
8D6<
B
VOLTAGE MONITOR AND RESET CIRCUIT
B
POWER BLOCK
PMC-Sierra, Inc.
A DRAWING TITLE=POWER_BLOCK ABBREV=POWER_BLOCK LAST_MODIFIED=Wed Feb DOCUMENT NUMBER: PMC-991724 ISSUE DATE: DOCUMENT ISSUE NUMBER: 1 *PRELIMINARY* NOV. 23, 99 TITLE: FREEDM-32P672 DS3 LIU REF. DESIGN POWER BLOCK 9 18:15:07 2000 ENGINEER: 10 9 8 7 6 5 4 3 TN 2 PAGE:9 1 OF 9 REVISION NUMBER: 0 A
PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
11
NO . 1 2 3 4 5 6
APPENDIX B: BILL OF MATERIALS
Part Number 21152 PI74FCT3244S MM74HC08M 78P2241 ELECTRO SONIC -- PC-834-J(BLACK) DIGI-KEY -PCC103BNCT-ND Manufact urer INTEL PERICOM FAIRCHIL D SEMI TDK SEMICOND UCTO R ? ? Ref Des U11 U2 U7 U1 "J2, J5" "C4-C6, C9-C11, C15-C65, C72, C74C104, C107, C108, C111, C112, C115, C116, C119, C120, C123, C124, C127" C7 Description PCI-TO-PCI BRIDGE HARDWARE FAST CMOS 3.3V 8BIT BUFFER/LINE DRIVER IC QUAD 2 IN AND GATE SOIC14 E3/DS3/STS-1 LINE INTERFACE TRANSCEIVER ? X7R DIELECTRIC Qty 1 1 1 1 2 100 Part Name - Value 21152_SOI C-BASE 74FCT3244 _SOICBASE 74XXX08_S OIC-HCMOS 78P2241_P LCC-BASE BANTAMBASE "CAPACITO R-0.01UF, 50V, X7R_805"
7
AVX -08055C473JATN
?
?
1
8
NEWARK -96F8740 DIGI-KEY -PCC1749CT-ND DIGI-KEY -PCT2106CT-ND
?
9
?
"C8, C12-C14, C73, C109" C68
X7R
6
X7R DIELECTRIC
1
10
?
"C69, C105"
PANASONIC TEH TANT. CAP.
2
"CAPACITO R0.047UF, 50V, X7R_805" "CAPACITO R-0.1UF, 50V, X7R_805" "CAPACITO R-0.22UF, 10V, X7R_603" "CAPACITO R-10UF, 10V, TANT TEH"
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
43
PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
11
DIGI-KEY -PCT2225CT-ND DIGI-KEY -PCT3226CT-ND DIGI-KEY -PCT1226CT-ND DIGI-KEY -PCT2475CT-ND DIGI-KEY -1N5820CT-ND PM7380 DIGIKEY -F1226CT-ND PZC36SAAN 1-644695-4 PZC36SAAN PZC36SAAN PZC36SAAN PZC36SAAN PZC36SAAN PZC36SAAN PZC36SAAN PZC36SAAN
?
C67
PANASONIC TEH TANT. CAP. PANASONIC TEH TANT. CAP. PANASONIC TEH TANT. CAP. PANASONIC TEH TANT. CAP. ?
1
12
?
"C70, C106" "C66, C71" C1-C3
2
13
?
2
14
?
3
15
?
D4
1
16 17
PMCSIERRA ?
U3 F1
FRAME ENGINE AND DATA LINK MANAGER 32P672 SOCKET PART NUMBER
1 1
18 19 20 21 22 23 24 25 26 27
SULLINS ELECTRON ICS AMP SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS SULLINS ELECTRON ICS
J12 J13 J11 J7 J8 J6 J10 J9 J1 J4
"CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" CONN MALE SINGLE ROW 14 PINS "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" "CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW"
1 1 1 1 1 1 1 1 1 1
"CAPACITO R-2.2UF, 10V, TANT TEH" "CAPACITO R-22UF, 16V, TANT TEH" "CAPACITO R-22UF, 6.3V, TANT TEH" "CAPACITO R-4.7UF, 10V, TANT TEH" "DIODE_SC HOTTKY_DO _20 1-3A, 20V" FREEDM32P 672_PBGABA SE "FUSE__SM D_SOCKET3.0 00A, NANO" HEADER10_ 100MILBASE HEADER14_ MALE-BASE HEADER2_1 00MILBASE HEADER2_1 00MILBASE HEADER2_1 00MILBASE HEADER2_1 00MILBASE HEADER2_1 00MILBASE HEADER2_1 00MILBASE HEADER4_1 00MILBASE HEADER4_1 00MILBASE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
44
PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
28 29 30
PZC36SAAN ? NEWARK -95F9373
SULLINS ELECTRON ICS ? ?
J3 J14 D1-D3
"CONN HEADER STRAIGHT 36POS MALE .1"" SINGLE ROW" HEADER 2X4 100MIL MALE IDI7002X5
1 1 3
31 32 33
LT1117CST-3.3 LT1118CST-2.5 MAX811S
LINEAR TECHNOLO GIES LINEAR TECHNOLO GIES MAXIM
U5 U8 U6
3.3V FIXED REGULATOR "REGULATOR, 2.5V, 800MA, POSITIVE, LOW DROPOUT" 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.3V SOT143 OSC HCMOS/TTL HALF SIZE 8 PIN 12.352MHZ 25PPM OSC HCMOS/TTL HALF SIZE 8 PIN 8.000MHZ 25PPM 2048 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8 "OSCILLATOR, 37.056MHZ, 3.3V, 32PPM" "OSCILLATOR, 44.736MHZ, 3.3V, 50PPM" VERT PCB MOUNT SPST PUSH BUTTOM PCI I/O ACCELERATOR ? ? ? ?
1 1 1
HEADER4_1 00MILBASE HEADER_4X 2_100MILBA SE "LEDSUPER_GRE EN, SURFACE MOUNT" LT1117_SO T-3.3V LT1118CST -2.5V MAX811S_S OT143BASE "MB3025H12.352MHZ , 25PPM" "MB3025H8.000MHZ, 25PPM" NM93CS56_ DIP8_SOCK ET -BASE "OSC_EP26 37.056MHZ , 3.3V, 32PPM" "OSC_EP26 44.736MHZ , 3.3V, 50PPM" PBNO_VERT _6MM-BASE PCI9054_P QFP-BASE PE65966BASE PE65969BASE "RESISTOR -1, 5%, 603" "RESISTOR -100K, 1%, 805"
34 35 36
MB3025H12.352MHZ MB3025H12.352MHZ NM93CS56LEN
MMD COMPONEN TS MMD COMPONEN TS FAIRCHIL D SEMI ECLIPTEK
Y3 Y4 U9
1 1 1
37
EP2632TTS37.056M
Y1
1
38
EP2645TTS44.736M
ECLIPTEK
Y2
1
39 40 41 42 43 44
DIGIKEY -P8009S-ND PCI9054-AA50PI PE65966 PE65969 ? DIGI-KEY -PCCT-ND
? PLX TECHNOLO GY ? ? ? ?
SW1 U10 T1 T2 R11 R7
1 1 1 1 1 1
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
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45 46 47 48 49
DIGI-KEY -PACT-ND DIGI-KEY -PACT-ND DIGI-KEY -PACT-ND DIGI-KEY -P301CCT-ND DIGI-KEY -PACT-ND
? ? ? ? ?
"R1-R6, R8, R12, R13" R100 R93 R14 "R25, R26, R56, R62-R64, R92, R168, R169" "R23, R24, R59, R104, R105, R108R110" R91 R10 "R15R22, R27-R55, R57, R58, R60, R61, R65-R90, R94-R99, R102, R103, R106, R107, R164" R9 "RN1RN10, RN12RN14, RN17, RN21" "RN11, RN15,
? ? ? ? ?
9 1 1 1 9
"RESISTOR -10K, 5%, 805" "RESISTOR -1K0, 5%, 805" "RESISTOR -220, 5%, 805" "RESISTOR -301, 1%, 805" "RESISTOR -330, 5%, 805"
50
DIGI-KEY -PACT-ND
?
?
8
"RESISTOR -4.7K, 5%, 805"
51 52 53
DIGI-KEY -PACT-ND DIGI-KEY -PCCT-ND DIGI-KEY -PACT-ND
? ? ?
? ? ?
1 1 78
"RESISTOR -470, 5%, 805" "RESISTOR -5.23K, 1%, 805" "RESISTOR -51, 5%, 805"
54 55
DIGI-KEY -P75.0CCT-ND DIGI-KEY -Y4-ND
? ?
? ?
1 15
"RESISTOR -75, 1%, 805" RES_ARRAY _4_SMD330
56
DIGI-KEY -Y4?
?
22
RES_ARRAY _4_SMD-
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
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CODE>-ND
57 58
PM8315-PI XC9536XL7PC44C
PMCSIERRA XILINX
RN16, RN18RN20, RN22RN37" U4 U12
4.7K
"T1/E1 FRAMER, VT/TU MAPPER, M13 MUX" IC IN SYSTEM PROGRAMMABLE CPLD PLCC44 SOCKETED
1 1
TEMUX_PBG A-BASE XC9536XL_ PC44_PLCC _S OCKETBASE
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
12
APPENDIX C: VHDL CODE FOR GLUE LOGIC CPLD code listing for interfacing the TEMUX and the PCI9054. Refer to the TEMUX micro interface timing diagrams in the TEMUX datasheet.
ENTITY TEMUX_9054 is PORT ( RESETB_9054: LCLK_CPLD: HOLD_9054: W_RB_9054: ADSB_9054: READYB_9054: INTB_9054: WRB_TEMUX: RDB_TEMUX: RSTB_TEMUX: CSB_TEMUX: INTB_TEMUX: ); END TEMUX_9054;
IN IN IN IN IN OUT OUT OUT OUT OUT OUT IN
STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;
-------------
reset from PCI9054 external 8MHz clock HOLD request from PCI9054 Write / Read from PCI9054 address strobe from PCI9054 Ready handshake to PCI9054 Interrupt to PCI9054 write strobe to TEMUX read strobe to TEMUX reset to TEMUX TEMUX chip select Interrupt from TEMUX
ARCHITECTUR TEMUX_9054 of TEMUX_9054 is COMPONENT BUFG -- global buffer component PORT (I: IN STD_LOGIC; O: OUT STD_LOGIC); END COMPONENT; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL BEGIN BUFG_1: BUFG_2: BUFG_3: BUFG BUFG BUFG PORT MAP (I => LCLK_CPLD, O => CLK); PORT MAP (I => RESETB_9054, O => RESET); PORT MAP (I => INTB_9054, O => INTB); falling: STD_LOGIC; rising: STD_LOGIC; CLK: STD_LOGIC; RESET: STD_LOGIC; INTB: STD_LOGIC; READ: STD_LOGIC; WRITE: STD_LOGIC;
RSTB_TEMUX <= RESET; INTB_TEMUX <= INTB;
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
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ADSB_FALLING: PROCESS(CLK, RESET) BEGIN IF (RESET = `0') THEN falling <= `1'; ELSIF (CLK = `0' AND CLK'EVENT) THEN falling <= ((NOT ADSB_9054) NAND HOLD_9054); END IF; END PROCESS ADSB_FALLING; ADSB_RISING: PROCESS(CLK, RESET) BEGIN IF (RESET = `0') THEN rising <= `1'; ELSIF (CLK = `1' AND CLK'EVENT) THEN rising <= falling; END IF; END PROCESS ADSB_RISING; READ_WRITE_CS: PROCESS(W_RB_9054) BEGIN IF (W_RB_9054 = '1') THEN CSB_TEMUX <= WRITE; ELSIF (W_RB_9054 = '0') THEN CSB_TEMUX <= READ; END IF; END PROCESS READ_WRITE_CS; READYB_9054 <= rising; WRITE <= ((NOT falling) NAND W_RB_9054); WRB_TEMUX <= WRITE; READ <= ((NOT rising) NAND (NOT W_RB_9054)); RDB_TEMUX <= READ; END TEMUX_9054;
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
NOTES
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PRELIMINARY PAPER REFERENCE DESIGN PMC-1991724 ISSUE 1
PMC-Sierra, Inc.
PM7380 FREEDM-32P672
FREEDM-32P672 WITH DS3 LIU REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990354 (P2) Issue date: August 1999
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